Inventor · disambiguated record
Hui Peng Koh
Also filed as: KOH HUI PENG
12 granted patents·2 pending applications·64 citations·filing 2005–2015
89Inventor score
Top patents by PatentIndex Score
14 records- 0191US7445978B2Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOSCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Nov 4, 2008·22 cites·31 claims
- 0284US7256084B2Composite stress spacerCHARTERED SEMICONDUCTOR MFG·Filed 2005·Granted Aug 14, 2007·12 cites·19 claims
- 0381US7745320B2Method for reducing silicide defects in integrated circuitsCHARTERED SEMICONDUCTOR MFG·Filed 2008·Granted Jun 29, 2010·7 cites·21 claims
- 0480US7892900B2Integrated circuit system employing sacrificial spacersGLOBALFOUNDRIES SG PTE LTD·Filed 2008·Granted Feb 22, 2011·9 cites·20 claims
- 0571US8624329B2Spacer-less low-K dielectric processesLEE YONG MENG·Filed 2009·Granted Jan 7, 2014·5 cites·18 claims
- 0669US7999325B2Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOSGLOBALFOUNDRIES SG PTE LTD·Filed 2008·Granted Aug 16, 2011·3 cites·20 claims
- 0768US9368453B2Overlay mark dependent dummy fill to mitigate gate height variationGLOBALFOUNDRIES INC·Filed 2015·Granted Jun 14, 2016·1 cites·15 claims
- 0868US7615427B2Spacer-less low-k dielectric processesCHARTERED SEMICONDUCTOR MFG·Filed 2006·Granted Nov 10, 2009·3 cites·20 claims
- 0967US8940641B1Methods for fabricating integrated circuits with improved patterning schemesGLOBALFOUNDRIES INC·Filed 2013·Granted Jan 27, 2015·2 cites·20 claims
- 1054US9252061B2Overlay mark dependent dummy fill to mitigate gate height variationGLOBALFOUNDRIES INC·Filed 2014·Granted Feb 2, 2016·0 cites·13 claims
- 1148US7960283B2Method for reducing silicide defects in integrated circuitsCHARTERED SEMICONDUCTOR MFG·Filed 2010·Granted Jun 14, 2011·0 cites·20 claims
- 1245US8911920B2Methods for fabricating EUV masks and methods for fabricating integrated circuits using such EUV masksGLOBALFOUNDRIES INC·Filed 2013·Granted Dec 16, 2014·0 cites·20 claims
- 1345US2008315317A1Semiconductor system having complementary strained channelsCHARTERED SEMICONDUCTOR MFG·Filed 2007·Application pending·0 cites
- 1440US2009179307A1Integrated circuit system employing feed-forward controlCHARTERED SEMICONDUCTOR MFG·Filed 2008·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →