Inventor · disambiguated record
Chok J. Chia
Also filed as: CHIA CHOK · CHIA CHOK J
73 granted patents·4 pending applications·2,945 citations·filing 1986–2024
99Inventor score
Top patents by PatentIndex Score
77 records- 0197US11929337B23D-interconnectINVENSAS LLC·Filed 2021·Granted Mar 12, 2024·3 cites·20 claims
- 0296US5814881AStacked integrated chip package and method of making sameLSI LOGIC CORP·Filed 1996·Granted Sep 29, 1998·229 cites·23 claims
- 0395US6081997ASystem and method for packaging an integrated circuit using encapsulant injectionLSI LOGIC CORP·Filed 1997·Granted Jul 4, 2000·202 cites·21 claims
- 0494US5973393AApparatus and method for stackable molded lead frame ball grid array packaging of integrated circuitsLSI LOGIC CORP·Filed 1996·Granted Oct 26, 1999·169 cites·4 claims
- 0594US5886398AMolded laminate package with integral mold gateLSI LOGIC CORP·Filed 1997·Granted Mar 23, 1999·184 cites·20 claims
- 0694US5435482AIntegrated circuit having a coplanar solder ball contact arrayLSI LOGIC CORP·Filed 1994·Granted Jul 25, 1995·145 cites·10 claims
- 0793US5728599APrintable superconductive leadframes for semiconductor device assemblyLSI LOGIC CORP·Filed 1995·Granted Mar 17, 1998·155 cites·9 claims
- 0890US6225695B1Grooved semiconductor die for flip-chip heat sink attachmentLSI LOGIC CORP·Filed 1997·Granted May 1, 2001·123 cites·16 claims
- 0989US4868349APlastic molded pin-grid-array power packageNAT SEMICONDUCTOR CORP·Filed 1988·Granted Sep 19, 1989·86 cites·7 claims
- 1088US10181447B23D-interconnectINVENSAS CORP·Filed 2017·Granted Jan 15, 2019·4 cites·14 claims
- 1188US6002169AThermally enhanced tape ball grid array packageLSI LOGIC CORP·Filed 1998·Granted Dec 14, 1999·114 cites·9 claims
- 1288US5557150AOvermolded semiconductor packageLSI LOGIC CORP·Filed 1995·Granted Sep 17, 1996·106 cites·6 claims
- 1388US5197183AModified lead frame for reducing wire wash in transfer molding of IC packagesLSI LOGIC CORP·Filed 1991·Granted Mar 30, 1993·107 cites·6 claims
- 1487US11031362B23D-interconnectINVENSAS CORP·Filed 2019·Granted Jun 8, 2021·3 cites·20 claims
- 1586US5923047ASemiconductor die having sacrificial bond pads for die testLSI LOGIC CORP·Filed 1997·Granted Jul 13, 1999·78 cites·3 claims
- 1685US12476212B23D-interconnectADEIA SEMICONDUCTOR TECH LLC·Filed 2024·Granted Nov 18, 2025·0 cites·12 claims
- 1785US9508687B2Low cost hybrid high density packageTESSERA INC·Filed 2015·Granted Nov 29, 2016·4 cites·16 claims
- 1885US5745986AMethod of planarizing an array of plastically deformable contacts on an integrated circuit package to compensate for surface warpageLSI LOGIC CORP·Filed 1995·Granted May 5, 1998·65 cites·10 claims
- 1985US5262927APartially-molded, PCB chip carrier packageLSI LOGIC CORP·Filed 1992·Granted Nov 16, 1993·85 cites·11 claims
- 2084US5434750APartially-molded, PCB chip carrier package for certain non-square die shapesLSI LOGIC CORP·Filed 1993·Granted Jul 18, 1995·68 cites·18 claims
- 2183US6519844B1Overmold integrated circuit packageLSI LOGIC CORP·Filed 2001·Granted Feb 18, 2003·36 cites·9 claims
- 2280US5841191ABall grid array package employing raised metal contact ringsLSI LOGIC CORP·Filed 1997·Granted Nov 24, 1998·58 cites·12 claims
- 2380US5744084AMethod of improving molding of an overmolded package body on a substrateLSI LOGIC CORP·Filed 1995·Granted Apr 28, 1998·54 cites·4 claims
- 2478US8963310B2Low cost hybrid high density packageDESAI Kishor·Filed 2011·Granted Feb 24, 2015·5 cites·16 claims
- 2578US5989937AMethod for compensating for bottom warpage of a BGA integrated circuitLSI LOGIC CORP·Filed 1997·Granted Nov 23, 1999·42 cites·9 claims
- 2677US6114189AMolded array integrated circuit packageLSI LOGIC CORP·Filed 1997·Granted Sep 5, 2000·51 cites·18 claims
- 2777US4688152AMolded pin grid array package GPTNAT SEMICONDUCTOR CORP·Filed 1986·Granted Aug 18, 1987·48 cites·3 claims
- 2875US5643835AProcess for manufacturing and mounting a semiconductor device leadframe having alignment tabsLSI LOGIC CORP·Filed 1996·Granted Jul 1, 1997·41 cites·6 claims
- 2975US5594626APartially-molded, PCB chip carrier package for certain non-square die shapesLSI LOGIC CORP·Filed 1995·Granted Jan 14, 1997·43 cites·30 claims
- 3074US5563446ASurface mount peripheral leaded and ball grid array packageLSI LOGIC CORP·Filed 1994·Granted Oct 8, 1996·39 cites·8 claims
- 3172US6088914AMethod for planarizing an array of solder ballsLSI LOGIC CORP·Filed 1997·Granted Jul 18, 2000·30 cites·56 claims
- 3272US5869889AThin power tape ball grid array packageLSI LOGIC CORP·Filed 1997·Granted Feb 9, 1999·43 cites·4 claims
- 3372US5353193AHigh power dissipating packages with matched heatspreader heatsink assembliesLSI LOGIC CORP·Filed 1993·Granted Oct 4, 1994·35 cites·18 claims
- 3471US6525421B1Molded integrated circuit packageLSI LOGIC CORP·Filed 2001·Granted Feb 25, 2003·18 cites·5 claims
- 3570US6743979B1Bonding pad isolationLSI LOGIC CORP·Filed 2003·Granted Jun 1, 2004·16 cites·20 claims
- 3670US5521427APrinted wiring board mounted semiconductor device having leadframe with alignment featureLSI LOGIC CORP·Filed 1994·Granted May 28, 1996·36 cites·15 claims
- 3768US6512293B1Mechanically interlocking ball grid array packages and method of makingLSI LOGIC CORP·Filed 2001·Granted Jan 28, 2003·15 cites·11 claims
- 3867US6963138B2Dielectric stackLSI LOGIC CORP·Filed 2003·Granted Nov 8, 2005·15 cites·20 claims
- 3966US4778641AMethod of molding a pin grid array packageNAT SEMICONDUCTOR CORP·Filed 1987·Granted Oct 18, 1988·31 cites·3 claims
- 4065US5933710AMethod of providing electrical connection between an integrated circuit die and a printed circuit boardLSI LOGIC CORP·Filed 1997·Granted Aug 3, 1999·26 cites·15 claims
- 4165US5927505AOvermolded package body on a substrateLSI LOGIC CORP·Filed 1997·Granted Jul 27, 1999·26 cites·4 claims
- 4265US5841198ABall grid array package employing solid core solder ballsLSI LOGIC CORP·Filed 1997·Granted Nov 24, 1998·32 cites·6 claims
- 4365US5270262AO-ring packageNAT SEMICONDUCTOR CORP·Filed 1991·Granted Dec 14, 1993·35 cites·11 claims
- 4465US5185653AO-ring packageNAT SEMICONDUCTOR CORP·Filed 1991·Granted Feb 9, 1993·34 cites·11 claims
- 4564US7646091B2Semiconductor package and method using isolated Vss plane to accommodate high speed circuitry ground isolationLSI CORP·Filed 2006·Granted Jan 12, 2010·3 cites·14 claims
- 4664US6054767AProgrammable substrate for array-type packagesLSI LOGIC CORP·Filed 1998·Granted Apr 25, 2000·26 cites·15 claims
- 4763US6306751B1Apparatus and method for improving ball joints in semiconductor packagesLSI LOGIC CORP·Filed 1999·Granted Oct 23, 2001·27 cites·11 claims
- 4862US5463529AHigh power dissipating packages with matched heatspreader heatsink assembliesLSI LOGIC CORP·Filed 1994·Granted Oct 31, 1995·24 cites·28 claims
- 4960US6670214B1Insulated bonding wire for microelectronic packagingLSI LOGIC CORP·Filed 2000·Granted Dec 30, 2003·9 cites·14 claims
- 5058US7327043B2Two layer substrate ball grid array designLSI LOGIC CORP·Filed 2005·Granted Feb 5, 2008·2 cites·12 claims
Showing the top 50 of 77 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →