Inventor · disambiguated record
Yannick Le Tiec
Also filed as: LE TIEC YANNICK · LE TIEC YANNICK C
22 granted patents·1 pending application·39 citations·filing 2007–2015
92Inventor score
Top patents by PatentIndex Score
23 records- 0190US9105691B2Contact isolation scheme for thin buried oxide substrate devicesIBM·Filed 2013·Granted Aug 11, 2015·11 cites·16 claims
- 0282US9601511B2Low leakage dual STI integrated circuit including FDSOI transistorsCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2013·Granted Mar 21, 2017·5 cites·14 claims
- 0382US9570465B2Dual STI integrated circuit including FDSOI transistors and method for manufacturing the sameCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2013·Granted Feb 14, 2017·6 cites·15 claims
- 0477US8530331B2Process for assembling substrates with low-temperature heat treatmentsBENEYTON REMI·Filed 2011·Granted Sep 10, 2013·3 cites·31 claims
- 0571US9076732B2Method to prepare semi-conductor device comprising a selective etching of a silicium—germanium layerCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2012·Granted Jul 7, 2015·2 cites·16 claims
- 0670US9236478B2Method for manufacturing a fin MOS transistorST MICROELECTRONICS SA·Filed 2014·Granted Jan 12, 2016·2 cites·25 claims
- 0769US9214515B2Method for making a semiconductor structure with a buried ground planeCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2013·Granted Dec 15, 2015·2 cites·14 claims
- 0868US9293474B2Dual channel hybrid semiconductor-on-insulator semiconductor devicesIBM·Filed 2015·Granted Mar 22, 2016·1 cites·14 claims
- 0967US8969966B2Defective P-N junction for backgated fully depleted silicon on insulator MOSFETIBM·Filed 2013·Granted Mar 3, 2015·1 cites·17 claims
- 1066US9337350B2Transistor with reduced parasitic capacitance and access resistance of the source and drain, and method of fabrication of the sameCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2012·Granted May 10, 2016·2 cites·15 claims
- 1166US9059041B2Dual channel hybrid semiconductor-on-insulator semiconductor devicesIBM·Filed 2013·Granted Jun 16, 2015·1 cites·10 claims
- 1265US9231062B2Method for treating the surface of a silicon substrateCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2013·Granted Jan 5, 2016·1 cites·20 claims
- 1361US8987854B2Microelectronic device with isolation trenches extending under an active areaCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2013·Granted Mar 24, 2015·1 cites·13 claims
- 1459US8722499B2Method for fabricating a field effect device with weak junction capacitanceVINET MAUD·Filed 2012·Granted May 13, 2014·1 cites·5 claims
- 1558US2009162991A1Process for assembling substrates with low-temperature heat treatmentsCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2007·Application pending·0 cites
- 1653US9373507B2Defective P-N junction for backgated fully depleted silicon on insulator mosfetGLOBALFOUNDRIES INC·Filed 2015·Granted Jun 21, 2016·0 cites·9 claims
- 1750US9673329B2Method for manufacturing a fin MOS transistorST MICROELECTRONICS SA·Filed 2015·Granted Jun 6, 2017·0 cites·12 claims
- 1848US8501588B2Method for making a semiconductor structure with a buried ground planeLE TIEC YANNICK·Filed 2009·Granted Aug 6, 2013·0 cites·16 claims
- 1947US8877618B2Method for producing a field effect transistor with a SiGe channel by ion implantationCOMMISSARIAT ENERGIE ATOMIQUE·Filed 2013·Granted Nov 4, 2014·0 cites·7 claims
- 2042US8994142B2Field effect transistor with offset counter-electrode contactVINET MAUD·Filed 2012·Granted Mar 31, 2015·0 cites·7 claims
- 2141US9437474B2Method for fabricating microelectronic devices with isolation trenches partially formed under active regionsGRENOUILLET LAURENT·Filed 2012·Granted Sep 6, 2016·0 cites·12 claims
- 2241US8735259B2Method of producing insulation trenches in a semiconductor on insulator substrateLE TIEC YANNICK·Filed 2012·Granted May 27, 2014·0 cites·7 claims
- 2336US9070709B2Method for producing a field effect transistor with implantation through the spacersPOSSEME NICOLAS·Filed 2011·Granted Jun 30, 2015·0 cites·15 claims
Join the waitlist — get patent alerts
Get an alert when Yannick Le Tiec files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →