Inventor · disambiguated record
Laura S. Chadwick
Also filed as: CHADWICK LAURA · CHADWICK LAURA S
9 granted patents·71 citations·filing 2002–2016
87Inventor score
Top patents by PatentIndex Score
9 records- 0181US7810054B2Method of optimizing power usage of an integrated circuit design by tuning selective voltage binning cut pointIBM·Filed 2008·Granted Oct 5, 2010·11 cites·6 claims
- 0278US7877714B2System and method to optimize semiconductor power by integration of physical design timing and product performance measurementsIBM·Filed 2008·Granted Jan 25, 2011·10 cites·7 claims
- 0377US7890906B2Method of laying out integrated circuit design based on known polysilicon perimeter densities of individual cellsIBM·Filed 2008·Granted Feb 15, 2011·8 cites·16 claims
- 0476US7487487B1Design structure for monitoring cross chip delay variation on a semiconductor deviceIBM·Filed 2008·Granted Feb 3, 2009·8 cites·1 claims
- 0575US7849433B2Integrated circuit with uniform polysilicon perimeter density, method and design structureIBM·Filed 2008·Granted Dec 7, 2010·7 cites·9 claims
- 0669US7073100B2Method for testing embedded DRAM arraysIBM·Filed 2002·Granted Jul 4, 2006·16 cites·10 claims
- 0763US7805693B2IC chip design modeling using perimeter density to electrical characteristic correlationIBM·Filed 2008·Granted Sep 28, 2010·2 cites·15 claims
- 0858US7237165B2Method for testing embedded DRAM arraysIBM·Filed 2004·Granted Jun 26, 2007·9 cites·18 claims
- 0940US9754071B1Integrated circuit (IC) design analysis and feature extractionGLOBALFOUNDRIES INC·Filed 2016·Granted Sep 5, 2017·0 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →