Inventor · disambiguated record
Takeshi Nagase
Also filed as: NAGASE TAKESHI
15 granted patents·2 pending applications·343 citations·filing 1979–2021
93Inventor score
Files withFUJITSU LTD7MITSUBISHI MOTORS CORP3YAMAHA MOTOR CO LTD3DEGUCHI CHIKAHIRO1FUJITSU MICROELECTRONICS LTD1
Top patents by PatentIndex Score
17 records- 0189US6154808AMethod and apparatus for controlling data erase operations of a non-volatile memory deviceFUJITSU LTD·Filed 1998·Granted Nov 28, 2000·82 cites·15 claims
- 0284US7117966B2Battery mounting arrangement for electrically powered vehicleYAMAHA MOTOR CO LTD·Filed 2003·Granted Oct 10, 2006·65 cites·15 claims
- 0384US6643730B2CPU controlled memory controlling device for accessing operational informationFUJITSU LTD·Filed 2001·Granted Nov 4, 2003·38 cites·8 claims
- 0483US4260170AMotorcycle having a leading axle type front fork assemblyYAMAHA MOTOR CO LTD·Filed 1979·Granted Apr 7, 1981·41 cites·2 claims
- 0580US7689836B2Encryption deviceFUJITSU MICROELECTRONICS LTD·Filed 2005·Granted Mar 30, 2010·11 cites·8 claims
- 0668US6418501B1Memory cardFUJITSU LTD·Filed 1999·Granted Jul 9, 2002·54 cites·8 claims
- 0764US6625712B2Memory management table producing method and memory deviceFUJITSU LTD·Filed 2001·Granted Sep 23, 2003·10 cites·17 claims
- 0851US6119801APower assisted bicycleYAMAHA MOTOR CO LTD·Filed 1997·Granted Sep 19, 2000·21 cites·33 claims
- 0950US8020736B2Spare tire cover supporting structureMITSUBISHI MOTORS CORP·Filed 2007·Granted Sep 20, 2011·1 cites·7 claims
- 1049US7168829B2Vehicle rear gateMITSUBISHI MOTORS CORP·Filed 2004·Granted Jan 30, 2007·6 cites·6 claims
- 1148US6449681B1Memory unit and buffer access control circuit for updating an address when consecutively accessing upper and lower buffersFUJITSU LTD·Filed 2001·Granted Sep 10, 2002·5 cites·6 claims
- 1246US2023220524A1Multi-component system alloyUNIV OSAKA·Filed 2021·Application pending·0 cites
- 1342US2007045361A1Spare tire cover mounting structureMITSUBISHI MOTORS CORP·Filed 2006·Application pending·0 cites
- 1435US6289411B1Circuit for generating a chip-enable signal for a multiple chip configurationFUJITSU LTD·Filed 1999·Granted Sep 11, 2001·7 cites·16 claims
- 1532US8143901B2Test apparatus, test method, and integrated circuitDEGUCHI CHIKAHIRO·Filed 2009·Granted Mar 27, 2012·0 cites·8 claims
- 1631US6339809B1Memory unit and buffer access control circuit for updating an address when consecutively accessing upper and lower buffersFUJITSU LTD·Filed 1999·Granted Jan 15, 2002·2 cites·2 claims
- 1728US8503259B2Memory test method and memory test deviceSHIBAZAKI SHOGO·Filed 2009·Granted Aug 6, 2013·0 cites·7 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →