Inventor · disambiguated record
Glen Andrew Harris
Also filed as: HARRIS GLEN A · HARRIS GLEN ANDREW
17 granted patents·5 pending applications·74 citations·filing 1996–2023
91Inventor score
Technology areasG06F
Files withADVANCED RISC MACH LTD13HARDAGE JAMES NOLAN4MOTOROLA INC3HARRIS GLEN ANDREW1HILL STEPHEN J1
Top patents by PatentIndex Score
22 records- 0177US8386754B2Renaming wide register source operand with plural short register source operands for select instructions to detect dependency fast with existing mechanismADVANCED RISC MACH LTD·Filed 2009·Granted Feb 26, 2013·9 cites·15 claims
- 0276US7234043B2Decoding predication instructions within a superscaler data processing systemADVANCED RISC MACH LTD·Filed 2005·Granted Jun 19, 2007·8 cites·11 claims
- 0372US7958335B2Multiple instruction set decodingADVANCED RISC MACH LTD·Filed 2005·Granted Jun 7, 2011·6 cites·17 claims
- 0464US9081581B2Size mis-match hazard detectionHARDAGE JAMES NOLAN·Filed 2010·Granted Jul 14, 2015·2 cites·19 claims
- 0564US7774582B2Result bypassing to override a data hazard within a superscalar processorADVANCED RISC MACH LTD·Filed 2005·Granted Aug 10, 2010·3 cites·10 claims
- 0657US7496899B2Preventing loss of traced information in a data processing apparatusADVANCED RISC MACH LTD·Filed 2005·Granted Feb 24, 2009·1 cites·23 claims
- 0755US12175251B2Compression of entries in a reorder bufferADVANCED RISC MACH LTD·Filed 2023·Granted Dec 24, 2024·0 cites·16 claims
- 0854US12204785B2Memcpy micro-operation reductionADVANCED RISC MACH LTD·Filed 2022·Granted Jan 21, 2025·0 cites·12 claims
- 0953US8914615B2Mapping same logical register specifier for different instruction sets with divergent association to architectural register file using common address formatHARRIS GLEN ANDREW·Filed 2011·Granted Dec 16, 2014·1 cites·23 claims
- 1051US2015082007A1Register mapping with multiple instruction setsADVANCED RISC MACH LTD·Filed 2014·Application pending·0 cites
- 1150US5822764AMethod and circuit for efficiently replacing invalid locked portions of a cache with valid dataMOTOROLA INC·Filed 1996·Granted Oct 13, 1998·23 cites·21 claims
- 1247US11204773B2Storing a processing state based on confidence in a predicted branch outcome and a number of recent state changesADVANCED RISC MACH LTD·Filed 2018·Granted Dec 21, 2021·0 cites·9 claims
- 1345US10310862B2Data processingADVANCED RISC MACH LTD·Filed 2017·Granted Jun 4, 2019·0 cites·10 claims
- 1444US11663014B2Speculatively executing instructions that follow a status updating instructionADVANCED RISC MACH LTD·Filed 2019·Granted May 30, 2023·0 cites·14 claims
- 1542US5911151AOptimizing block-sized operand movement utilizing standard instructionsMOTOROLA INC·Filed 1996·Granted Jun 8, 1999·15 cites·19 claims
- 1642US2007043930A1Performance of a data processing apparatusHILL STEPHEN J·Filed 2005·Application pending·0 cites
- 1742US2006218124A1Performance of a data processing apparatusADVANCED RISC MACH LTD·Filed 2005·Application pending·0 cites
- 1842US2007028078A1Instruction queues in pipelined processorsADVANCED RISC MACH LTD·Filed 2005·Application pending·0 cites
- 1939US8972701B2Setting zero bits in architectural register for storing destination operand of smaller size based on corresponding zero flag attached to renamed physical registerHARDAGE JAMES NOLAN·Filed 2011·Granted Mar 3, 2015·0 cites·21 claims
- 2038US2012124346A1Decoding conditional program instructionsHARDAGE JAMES NOLAN·Filed 2010·Application pending·0 cites
- 2137US9946545B2Buffer store with a main store and and auxiliary storeHARDAGE JAMES NOLAN·Filed 2010·Granted Apr 17, 2018·0 cites·15 claims
- 2233US5781916ACache control circuitry and method thereforMOTOROLA INC·Filed 1996·Granted Jul 14, 1998·6 cites·6 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →