Register mapping with multiple instruction sets

Abstract

A processor core supports execution of program instruction from both a first instruction set and a second instruction set. An architectural register file 18 containing architectural registers is shared by the two instruction sets. The two instruction sets employ logical register specifiers which for at least some values of those logical registers specifiers correspond to different architectural registers within the architectural register file 18. A first decoder 4 for the first instruction set and a second decoder 6 for the second instruction set serve to decode the logical register specifiers to a common register addressing format. This common register addressing format is used to supply register specifiers to renaming circuitry 10 for supporting register renaming in conjunction with a physical register file 16 and an architectural register file 18.

We claim: 
     
         1 . Apparatus for processing data comprising:
 a register file having a plurality of registers for storing operand values;   first decoder circuitry configured to decode program instructions of a first instruction set; and   second decoder circuitry configured to decode program instructions of a second instruction set; wherein   program instructions of said first instruction set include first logical register specifiers;   program instructions of said second instruction set include second logical register specifiers;   said first decoder circuitry is configured to map said first logical specifiers using a first mapping to a common address format;   said second decoder circuitry is configured to map said second logical specifiers using a second mapping to said common address format; and   said second mapping is divergent from said first mapping such that at least some values used as both a first logical register specifier and a second logical register specifier map to different registers.   
     
     
         2 . Apparatus as claimed in  claim 1 , wherein said plurality of registers are addressed as an array of architectural registers arranged in a plurality of banks and a plurality of rows and said common address format comprises a bank specifier and a row specifier within said array. 
     
     
         3 . Apparatus as claimed in  claim 2 , wherein said plurality of banks permit first logical registers and second logical registers having said maximum number of words to be stored in a single row of said array. 
     
     
         4 . Apparatus as claimed in  claim 1 , wherein said first logical register specifiers specify first logical registers corresponding to architectural registers within said register file having a plurality of different sizes corresponding to different numbers of words of data up to a maximum number of words of data; and
 one of said first logical registers of said maximum number of words corresponds to a group of architectural registers that are all mapped by said first mapping to a plurality of first logical registers at each different lower size.   
     
     
         5 . Apparatus as claimed in  claim 1 , wherein
 said second logical register specifiers specify second logical registers corresponding to architectural registers within said register file having a plurality of different sizes corresponding to different numbers of words of data up to said maximum number of words of data; and   one of said second logical registers of said maximum number of words corresponds to a group of architectural registers that at least one of which is mapped by said second mapping to a single second logical register at each different lower size.   
     
     
         6 . Apparatus as claimed in  claim 1 , comprising a plurality of physical registers configured to store data values to be manipulated and renaming circuitry configured to store register mapping data mapping between a bank specifier value and a row specifier value identifying an architectural register and one of said physical registers to be used in place of said architectural register for speculative execution of a program instruction. 
     
     
         7 . Apparatus as claimed in  claim 1 , wherein a plurality of architectural registers corresponding to one of a first logical register or a second logical register is identified with register specifying signals transferred within said apparatus identifying a single architectural register value in said common address format and a size qualifier value. 
     
     
         8 . Apparatus as claimed in  claim 1 , wherein first logical registers corresponding to said first logical register specifiers have a size of any of a single word of data, a double word of data and a quad word of data. 
     
     
         9 . Apparatus as claimed in  claim 4 , wherein said first logical registers have a size of any of a single word of data, a double word of data and a quad word of data and said group of architectural registers corresponds to four first logical registers of a single word of data, two first logical registers of a double word of data and one first logical register of a quad word of data. 
     
     
         10 . Apparatus as claimed in  claim 1 , wherein said second logical registers corresponding to said second logical register specifiers have a size of any of a single word of data, a double word of data and a quad word of data. 
     
     
         11 . Apparatus as claimed in  claim 5 , wherein said second logical registers have a size of any of a single word of data, a double word of data and a quad word of data and said group of architectural registers corresponds to four second logical registers of a single word of data, two second logical registers of a double word of data and one second logical register of a quad word of data. 
     
     
         12 . Apparatus for processing data comprising:
 a plurality of register means for storing operand values;   first decoder means for decoding program instructions of a first instruction set; and   second decoder means for decoding program instructions of a second instruction set; wherein   program instructions of said first instruction set include first logical register specifiers;   program instructions of said second instruction set include second logical register specifiers;   said first decoder means maps said first logical specifiers using a first mapping to a common address format;   said second decoder means maps said second logical specifiers using a second mapping to said common address format; and   said second mapping is divergent from said first mapping such that at least some values used as both a first logical register specifier and a second logical register specifier map to different register means.   
     
     
         13 . A method of processing data comprising the steps of:
 performing processing operations with processing circuitry;   storing operand values in a plurality of registers of a register file;   decoding program instructions of a first instruction set; and   decoding program instructions of a second instruction set; wherein   program instructions of said first instruction set include first logical register specifiers;   program instructions of said second instruction set include second logical register specifiers;   
       further comprising the steps of:
 using a first mapping to map said first logical specifiers to a common address format; and 
 using a second mapping to map said second logical specifiers to said common address format; wherein 
 said second mapping is divergent from said first mapping such that at least some values used as both a first logical register specifier and a second logical register specifier map to different registers. 
 
     
     
         14 . A method as claimed in  claim 13 , comprising the steps of addressing said plurality of register as an array of architectural registers arranged in a plurality of banks and a plurality of rows and said common address format comprises a bank specifier and a row specifier within said array. 
     
     
         15 . A method as claimed in  claim 14 , wherein said plurality of banks permit first logical registers and second logical registers having said maximum number of words to be stored in a single row of said array. 
     
     
         16 . A method as claimed in  claim 13 , wherein said first logical register specifiers specify first logical registers corresponding to architectural registers within said register file having a plurality of different sizes corresponding to different numbers of words of data up to a maximum number of words of data; and one of said first logical registers of said maximum number of words corresponds to a group of architectural registers that are all mapped by said first mapping to a plurality of first logical registers at each different lower size. 
     
     
         17 . A method as claimed in  claim 13 , wherein said second logical register specifiers specify second logical registers corresponding to architectural registers within said register file having a plurality of different sizes corresponding to different numbers of words of data up to said maximum number of words of data; one of said second logical registers of said maximum number of words corresponds to a group of architectural registers that at least one of which is mapped by said second mapping to a single second logical register at each different lower size. 
     
     
         18 . A method as claimed in  claim 13 , comprising the steps of storing data values to be manipulated in a plurality of physical registers and storing register mapping data mapping between a bank specifier value and a row specifier value identifying an architectural register and one of said physical registers to be used in place of said architectural register for speculative execution of a program instruction. 
     
     
         19 . A method as claimed in  claim 13 , comprising the step of identifying a plurality of architectural registers corresponding to one of a first logical register or a second logical register with register specifying signals identifying a single architectural register value in said common address format and a size qualifier value. 
     
     
         20 . A method as claimed in  claim 13 , wherein first logical registers corresponding to said first logical register specifiers have a size of any of a single word of data, a double word of data and a quad word of data. 
     
     
         21 . A method as claimed in  claim 16 , wherein said first logical registers have a size of any of a single word of data, a double word of data and a quad word of data and said group of architectural registers corresponds to four first logical registers of a single word of data, two first logical registers of a double word of data and one first logical register of a quad word of data. 
     
     
         22 . A method as claimed in  claim 12 , wherein second logical registers corresponding to said second logical register specifiers have a size of any of a single word of data, a double word of data and a quad word of data. 
     
     
         23 . A method as claimed in  claim 17 , wherein said second logical registers have a size of any of a single word of data, a double word of data and a quad word of data and said group of architectural registers corresponds to four second logical registers of a single word of data, two second logical registers of a double word of data and one second logical register of a quad word of data.