Inventor · disambiguated record
Krishnan S. Rengarajan
Also filed as: RENGARAJAN KRISHNAN · RENGARAJAN KRISHNAN S · RENGARAJAN KRISHNAN SANTHANA
33 granted patents·237 citations·filing 2001–2019
97Inventor score
Top patents by PatentIndex Score
33 records- 0194US9496025B2Tunable negative bitline write assist and boost attenuation circuitIBM·Filed 2015·Granted Nov 15, 2016·20 cites·17 claims
- 0294US9236116B1Memory cells with read access schemesIBM·Filed 2015·Granted Jan 12, 2016·24 cites·20 claims
- 0393US10659017B1Low-power scan flip-flopMARVELL INT LTD·Filed 2018·Granted May 19, 2020·15 cites·20 claims
- 0493US9548104B1Boost control to improve SRAM write operationIBM·Filed 2015·Granted Jan 17, 2017·15 cites·20 claims
- 0589US8427896B1Dynamic wordline assist scheme to improve performance tradeoff in SRAMAGARWAL PANKAJ·Filed 2011·Granted Apr 23, 2013·25 cites·20 claims
- 0688US10840892B1Fully digital, static, true single-phase clock (TSPC) flip-flopMARVELL INT LTD·Filed 2019·Granted Nov 17, 2020·8 cites·21 claims
- 0788US9460760B2Data-dependent self-biased differential sense amplifierGLOBALFOUNDRIES INC·Filed 2015·Granted Oct 4, 2016·11 cites·25 claims
- 0888US9281045B1Refresh hidden eDRAM memoryIBM·Filed 2014·Granted Mar 8, 2016·11 cites·12 claims
- 0986US10447510B1On-demand feed forward equalizer with distributed arithmetic architecture and methodGLOBALFOUNDRIES INC·Filed 2019·Granted Oct 15, 2019·10 cites·20 claims
- 1086US10432436B1Feed forward equalizer with power-optimized distributed arithmetic architecture and methodGLOBALFOUNDRIES INC·Filed 2018·Granted Oct 1, 2019·5 cites·20 claims
- 1186US9847119B2Tunable negative bitline write assist and boost attenuation circuitIBM·Filed 2016·Granted Dec 19, 2017·5 cites·14 claims
- 1285US9047980B2Sense amplifier for static random access memory with a pair of complementary data lines isolated from a corresponding pair of complementary bit linesAGARWAL PANKAJ·Filed 2012·Granted Jun 2, 2015·14 cites·23 claims
- 1384US7142466B1Determining optimal time instances to sense the output of a memory array which can generate data outputs with variable delayTEXAS INSTRUMENTS INC·Filed 2005·Granted Nov 28, 2006·24 cites·16 claims
- 1482US9286969B2Low power sense amplifier for static random access memoryGLOBALFOUNDRIES INC·Filed 2014·Granted Mar 15, 2016·10 cites·18 claims
- 1581US9251890B1Bias temperature instability state detection and correctionGLOBALFOUNDRIES INC·Filed 2014·Granted Feb 2, 2016·7 cites·20 claims
- 1676US9437282B1High performance sense amplifierGLOBALFOUNDRIES INC·Filed 2015·Granted Sep 6, 2016·4 cites·20 claims
- 1773US9984742B2Tunable negative bitline write assist and boost attenuation circuitIBM·Filed 2016·Granted May 29, 2018·2 cites·11 claims
- 1871US7372713B2Match sensing circuit for a content addressable memory deviceTEXAS INSTRUMENTS INC·Filed 2006·Granted May 13, 2008·9 cites·17 claims
- 1969US9570155B2Circuit to improve SRAM stabilityIBM·Filed 2015·Granted Feb 14, 2017·3 cites·3 claims
- 2068US9589658B1Disturb free bitcell and arrayGLOBALFOUNDRIES INC·Filed 2015·Granted Mar 7, 2017·3 cites·20 claims
- 2167US10217510B2Tunable negative bitline write assist and boost attenuation circuitIBM·Filed 2017·Granted Feb 26, 2019·1 cites·7 claims
- 2260US7755949B2Reset circuit for termination of tracking circuits in self timed compiler memoriesTEXAS INSTRUMENTS INC·Filed 2008·Granted Jul 13, 2010·4 cites·10 claims
- 2355US10783958B2Tunable negative bitline write assist and boost attenuation circuitIBM·Filed 2019·Granted Sep 22, 2020·0 cites·11 claims
- 2454US10783956B2Tunable negative bitline write assist and boost attenuation circuitIBM·Filed 2019·Granted Sep 22, 2020·0 cites·18 claims
- 2552US9324430B2Method for defining a default state of a charge trap based memory cellGLOBALFOUNDRIES INC·Filed 2014·Granted Apr 26, 2016·1 cites·7 claims
- 2651US10721104B2Feed forward equalizer with power-optimized distributed arithmetic architecture and methodMARVELL INT LTD·Filed 2019·Granted Jul 21, 2020·0 cites·19 claims
- 2751US10489455B2Scoped search engineIBM·Filed 2014·Granted Nov 26, 2019·0 cites·20 claims
- 2851US10319431B2Tunable negative bit line write assist and boost attenuation circuitIBM·Filed 2017·Granted Jun 11, 2019·0 cites·9 claims
- 2951US7006585B2Recovering data encoded in serial communication channelsTEXAS INSTRUMENTS INC·Filed 2001·Granted Feb 28, 2006·1 cites·4 claims
- 3046US9859873B2Minimization of bias temperature instability (BTI) degradation in circuitsIBM·Filed 2014·Granted Jan 2, 2018·0 cites·3 claims
- 3141US6563386B1Self-starter for PLL synthesizersTEXAS INSTRUMENTS INC·Filed 2001·Granted May 13, 2003·5 cites·19 claims
- 3240US8593861B2Asymmetric memory cellsBRACERAS GEORGE M·Filed 2011·Granted Nov 26, 2013·0 cites·20 claims
- 3335US8797096B2Crosstalk compensation for high speed, reduced swing circuitsNALAWADE PRASAD S·Filed 2011·Granted Aug 5, 2014·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →