Assignee
MURALIMANOHAR NAVEEN
US10 patents
Top patents by PatentIndex Score
US9361955B2Jun 7, 2016
Memory access methods and apparatus
MURALIMANOHAR NAVEEN15 citations91
US8938589B2Jan 20, 2015
Interface methods and apparatus for memory devices using arbitration
MURALIMANOHAR NAVEEN5 citations84
US8638600B2Jan 28, 2014
Random-access memory with dynamically adjustable endurance and retention
MURALIMANOHAR NAVEEN9 citations84
US8537634B2Sep 17, 2013
Parallelized check pointing using MATs and through silicon VIAs (TSVs)
MURALIMANOHAR NAVEEN10 citations84
US9443580B2Sep 13, 2016
Multi-level cell memory
MURALIMANOHAR NAVEEN7 citations83
US8108718B2Jan 31, 2012
Checkpointing in massively parallel processing
MURALIMANOHAR NAVEEN6 citations73
US8661298B2Feb 25, 2014
Controlling nanostore operation based on monitored performance
MURALIMANOHAR NAVEEN2 citations62
US9003247B2Apr 7, 2015
Remapping data with pointer
MURALIMANOHAR NAVEEN1 citations52
US8990646B2Mar 24, 2015
Memory error test routine
MURALIMANOHAR NAVEEN0 citations52
US8892808B2Nov 18, 2014
Retention-value associated memory
MURALIMANOHAR NAVEEN0 citations41