Row shifting shiftable memory

Abstract

A shiftable memory employs row shifting to shift data along a row. The shiftable memory includes memory cells arranged as a plurality of rows and a plurality of columns. The shiftable memory further includes shift logic to shift data from an output of a first column to an input of a second column. The shifted data is provided by a memory cell of the first column in a selected row. The shifted data is received and stored by a memory cell in the selected row of the second column. The shift logic facilitates shifting data along the selected row.

What is claimed is: 
     
         1 . A shiftable memory comprising:
 memory cells arranged as a plurality of rows and a plurality of columns; and   shift logic to shift data from an output of a first column to an input of a second column, the shifted data being provided by a memory cell of the first column in a selected row and the shifted data being received and stored by a memory cell in the selected row of the second column,   wherein the shift logic is to facilitate shifting data along the selected row.   
     
     
         2 . The shiftable memory of  claim 1 , wherein the first column and the second column are adjacent to one another and all of the data within the selected row is shifted by the shift logic. 
     
     
         3 . The shiftable memory of  claim 1 , wherein a number of columns between the first column and the second column is selectable between zero and a number that is less than a total number of columns of the shiftable memory. 
     
     
         4 . The shiftable memory of  claim 1 , wherein the shift logic is to shift the data in a direction along the selected row that is one of toward a beginning of the selected row and toward an end of the selected row. 
     
     
         5 . The shiftable memory of  claim 1 , wherein the shift logic comprises a multiplexer having an input connected to the output of the first column and having a multiplexer output connected to the input of the second column, the multiplexer to select between data from another input of the multiplexer and data on the first column output, and further the multiplexer to route the selected data to the input of the second column for storage in the memory cell in the selected row of the second column. 
     
     
         6 . The shiftable memory of  claim 1 , further comprising one or both of a sense amplifier and an bit line driver on bit lines of the first column and the second column, the sense amplifier and the bit line driver being between the plurality of rows of memory cells and the shift logic. 
     
     
         7 . The shiftable memory of  claim 6 , wherein the shift logic comprises a multiplexer connected to selectively route data produced at an output of the sense amplifier of the bit line of the first column to an input of the bit line driver of the bit line of the second column, the multiplexer to selectively route data when data is to be shifted. 
     
     
         8 . The shiftable memory of  claim 1 , wherein the memory cell comprises one of a dynamic random access memory (DRAM) memory cell and a static random access memory (SRAM) memory cell, the output and the input of the columns comprising bit lines associated with either the DRAM memory cell or the SRAM memory cell. 
     
     
         9 . The shiftable memory of  claim 1 , further comprising a controller one or both of to select the rows using word lines associated with the rows and to control the shift logic to facilitate shifting data. 
     
     
         10 . A shiftable memory system comprising:
 an array of memory cells arranged in rows and columns, memory cells of each row being connected in common to a word line of the row and memory cells of the columns being connected in common to a bit line of the column;   a plurality of shift circuits, a shift circuit of the plurality being connected between a first column bit line and a second column bit line to shift data output by the first column into the second column, the shifted data to be stored in a memory cell in unelected row of the second column; and   a controller to select the rows using the word lines and to control the shift logic circuit to facilitate shifting data.   
     
     
         11 . The shiftable memory system of  claim 10 , further comprising one or both of a sense amplifier and a bit line driver between the array of memory cells and the shift circuits, the sense amplifier to produce the output data from a signal on the first bit line generated by a memory cell of the first column in the selected row and the bit line driver to provide the output data to the memory cell in the selected row of the second column. 
     
     
         12 . The shiftable memory system of  claim 10 , wherein the memory cell comprises one of a dynamic random access memory (DRAM) memory cell and a static random access memory (SRAM) memory cell, the bit lines comprising pairs of bit lines associated with either the DRAM memory cell or the SRAM memory cell. 
     
     
         13 . The shiftable memory system of  claim 10 , wherein the data comprises data words, the data words being stored one of sequentially along one or more of the rows of the plurality and distributed across a plurality of adjacent arrays in corresponding rows. 
     
     
         14 . A method of shifting data in a shiftable memory, the method comprising:
 selecting a row of memory cells of the shiftable memory, the memory cells of the shiftable memory being arranged as a plurality of rows and a plurality of columns;   communicating data between columns using shift logic of the shiftable memory, communicating data being from a first column to a second column, the data being provided by a memory cell of the first column in the selected row; and   storing the communicated data in a memory cell of a second column in the selected row,   wherein the communicated data is shifted along the selected row from the first column memory cell to the second column memory cell.   
     
     
         15 . The method of shifting data in shiftable memory of  claim 14 , wherein communicating data between columns comprises:
 amplifying a signal on a bit line from the memory cell of the first column using a sense amplifier to produce the data at an output of the sense amplifier;   selectively transferring the data from the output of the sense amplifier to an input of a bit line driver of the second column; and   driving the bit line of the second column using the bit line driver to produce a signal that facilitates storing the data in the memory cell of the second column in the selected row,   wherein selectively transferring the data is performed by shift logic of the shiftable memory when data is shifted.