Individual holder
DOYLE BRIAN S
US·17 granted patents·17 pending applications·195 citations·filing 2004–2015
Individually held — no corporate assignee on record.
Top patents by PatentIndex Score
34 records- 0198US8294180B2CMOS devices with a single work function gate electrode and method of fabricationDOYLE BRIAN S·Filed 2011·Granted Oct 23, 2012·37 cites·14 claims
- 0297US8890119B2Vertical nanowire transistor with axially engineered semiconductor and gate metallizationDOYLE BRIAN S·Filed 2012·Granted Nov 18, 2014·31 cites·18 claims
- 0395US9306063B2Vertical transistor devices for embedded memory and logic technologiesDOYLE BRIAN S·Filed 2013·Granted Apr 5, 2016·20 cites·19 claims
- 0495US8796797B2Perpendicular spin transfer torque memory (STTM) device with enhanced stability and method to form sameDOYLE BRIAN S·Filed 2012·Granted Aug 5, 2014·17 cites·30 claims
- 0594US8169027B2Substrate band gap engineered multi-gate pMOS devicesDOYLE BRIAN S·Filed 2010·Granted May 1, 2012·16 cites·17 claims
- 0693US8148772B2Recessed channel array transistor (RCAT) structuresDOYLE BRIAN S·Filed 2011·Granted Apr 3, 2012·14 cites·14 claims
- 0792US8786040B2Perpendicular spin transfer torque memory (STTM) device having offset cells and method to form sameDOYLE BRIAN S·Filed 2012·Granted Jul 22, 2014·12 cites·28 claims
- 0892US8138042B2Capacitor, method of increasing a capacitance area of same, and system containing sameDOYLE BRIAN S·Filed 2010·Granted Mar 20, 2012·12 cites·12 claims
- 0987US9166150B2Electric field enhanced spin transfer torque memory (STTM) deviceDOYLE BRIAN S·Filed 2012·Granted Oct 20, 2015·9 cites·24 claims
- 1087US8519510B2Semiconductor structure having an integrated quadruple-wall capacitor for embedded dynamic random access memory (eDRAM) and method to form the sameDOYLE BRIAN S·Filed 2011·Granted Aug 27, 2013·9 cites·15 claims
- 1185US9054302B2Perpendicular spin transfer torque memory (STTM) device with enhanced stability and method to form sameDOYLE BRIAN S·Filed 2014·Granted Jun 9, 2015·6 cites·5 claims
- 1276US10541014B2Memory cells with enhanced tunneling magnetoresistance ratio, memory devices and systems including the sameDOYLE BRIAN S·Filed 2015·Granted Jan 21, 2020·4 cites·21 claims
- 1374US9711284B2Structure to make supercapacitorDOYLE BRIAN S·Filed 2012·Granted Jul 18, 2017·2 cites·14 claims
- 1474US8232588B2Increasing the surface area of a memory cell capacitorDOYLE BRIAN S·Filed 2010·Granted Jul 31, 2012·3 cites·6 claims
- 1571US8796794B2Write current reduction in spin transfer torque memory devicesDOYLE BRIAN S·Filed 2010·Granted Aug 5, 2014·3 cites·9 claims
- 1653US2009179282A1Metal gate device with reduced oxidation of a high-k gate dielectricDOYLE BRIAN S·Filed 2009·Application pending·0 cites
- 1749US9105839B2Perpendicular spin transfer torque memory (STTM) device having offset cells and method to form sameDOYLE BRIAN S·Filed 2014·Granted Aug 11, 2015·0 cites·5 claims
- 1848US2009001438A1Isolation of MIM FIN DRAM capacitorDOYLE BRIAN S·Filed 2007·Application pending·0 cites
- 1947US2007090416A1CMOS devices with a single work function gate electrode and method of fabricationDOYLE BRIAN S·Filed 2005·Application pending·0 cites
- 2046US2009057846A1Method to fabricate adjacent silicon fins of differing heightsDOYLE BRIAN S·Filed 2007·Application pending·0 cites
- 2146US2007235763A1Substrate band gap engineered multi-gate pMOS devicesDOYLE BRIAN S·Filed 2006·Application pending·0 cites
- 2246US2009004868A1Amorphous silicon oxidation patterningDOYLE BRIAN S·Filed 2007·Application pending·0 cites
- 2345US2011260244A1Recessed channel array transistor (rcat) in replacement metal gate (rmg) logic flowDOYLE BRIAN S·Filed 2011·Application pending·0 cites
- 2444US2010258908A1Isolation of mim fin dram capacitorDOYLE BRIAN S·Filed 2010·Application pending·0 cites
- 2544US2010155801A1Integrated circuit, 1T-1C embedded memory cell containing same, and method of manufacturing 1T-1C memory cell for embedded memory applicationDOYLE BRIAN S·Filed 2008·Application pending·0 cites
- 2643US2009206405A1Fin field effect transistor structures having two dielectric thicknessesDOYLE BRIAN S·Filed 2008·Application pending·0 cites
- 2743US2009108313A1Reducing short channel effects in transistorsDOYLE BRIAN S·Filed 2007·Application pending·0 cites
- 2842US2008237672A1High density memoryDOYLE BRIAN S·Filed 2007·Application pending·0 cites
- 2941US2008157162A1Method of combining floating body cell and logic transistorsDOYLE BRIAN S·Filed 2006·Application pending·0 cites
- 3041US2008237719A1Multi-gate structure and method of doping sameDOYLE BRIAN S·Filed 2007·Application pending·0 cites
- 3140US2012235274A1Semiconductor structure having an integrated double-wall capacitor for embedded dynamic random access memory (edram) and method to form the sameDOYLE BRIAN S·Filed 2011·Application pending·0 cites
- 3239US9793467B2Method for reducing size and center positioning of magnetic memory element contactsDOYLE BRIAN S·Filed 2011·Granted Oct 17, 2017·0 cites·7 claims
- 3338US2006091467A1Resonant tunneling device using metal oxide semiconductor processingDOYLE BRIAN S·Filed 2004·Application pending·0 cites
- 3434US2014204661A1Memory with elements having two stacked magnetic tunneling junction (mtj) devicesDOYLE BRIAN S·Filed 2011·Application pending·0 cites
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