Metal gate device with reduced oxidation of a high-k gate dielectric

Abstract

Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer and reduced oxidation of a substrate beneath the high-k gate dielectric layer. An oxygen barrier, or capping, layer on the high-k gate dielectric layer and metal gate may prevent such oxidation during processes such as spacer formation and annealing of ion implanted regions.

1 . A semiconductor device, comprising:
 a substrate;   a high-k gate dielectric layer on the substrate;   a metal gate electrode on the high-k gate dielectric layer; and   a capping layer that is substantially free of oxygen and substantially seals a region between the high-k gate dielectric layer and the substrate from structures that comprise oxygen.   
   
   
       2 . The device of  claim 1 , further comprising:
 a first set of spacers on either side of the metal gate electrode;   a second set of spacers on either side of the first set of spacers; and   wherein the capping layer is between the first set of spacers and the second set of spacers.   
   
   
       3 . The device of  claim 2 , wherein the second set of spacers have a bottom surface and the capping layer extends beneath the bottom surface of the second set of spacers. 
   
   
       4 . The device of  claim 1 , further comprising a thin oxide layer between the high-k gate dielectric layer and the substrate and a first set of spacers on either side of the metal gate electrode, wherein the first set of spacers have a bottom surface and the thin oxide layer extends beneath the bottom surface of the first set of spacers. 
   
   
       5 . The device of  claim 1 , wherein the capping layer comprises a nitride material. 
   
   
       6 . The device of  claim 5 , wherein the capping layer has a thickness below about 75 angstroms. 
   
   
       7 . The device of  claim 5 , wherein the capping layer comprises a material selected from the group consisting of 8-12% carbon-doped silicon nitride, stoichiometric silicon nitride and silicon carbide. 
   
   
       8 . The device of  claim 2 , wherein the second set of spacers have a bottom surface and the capping layer extends beneath the bottom surface of the second set of spacers.