Semiconductor memory device

Abstract

A CRC code is generated from an original data, a BCH code is generated with respect to the original data and the CRC code, and the original data, the CRC code, and the BCH code are recorded in pages selected from different planes of a plurality of memory chips. An RS code is generated from the original data across pages, a CRC code is generated with respect to the RS code, a BCH code is generated with respect to the RS code and the CRC code, and the RS code, the CRC code, the BCH code are recorded in a memory chip different from a memory chip including the original data. When reading data, error correction is performed on the original data by using the BCH code, and then CRC is calculated. If the number of errors is the number of errors that is correctable by erasure correction using the RS code, the original data is corrected by the erasure correction. If the number of errors exceeds an erasure correction capability of the RS code, normal error correction using the RS code is performed, and further error correction using the BCH code is performed.

What is claimed is: 
     
         1 . A semiconductor memory device comprising:
 a memory chip;   a first encoder/decoder (E/D) configured to obtain a first error check code and a first error correction code based on an original data, the original data, the first error check code, and the first error correction code are recorded on a first page of a memory chip;   an encoder configured to obtain a second error correction code for the original data, the type of the second error correction is different from the type of the first error correction; and   a second E/D configured to obtain a second error check code and a third error correction code based on the second error correction code wherein, the second error correction code, the second error check code, and the third error correction code are recorded on a second page of a memory chip.   
     
     
         2 . The device of  claim 1 , wherein
 the first E/D obtains the first error check code based on the original data and obtains the first error correction code based on the original data and the first error check code, and the second E/D obtains the second error check code based on the second error correction code and obtains the third error correction code based on the second error correction code and the second error check code.   
     
     
         3 . The device of  claim 2 , wherein
 a size of a data block of the original data and a size of a data block of the second error correction code are the same.   
     
     
         4 . The device of  claim 3 , wherein
 the second error correction code is formed across a plurality of pages in a direction crossing data blocks of the original data.   
     
     
         5 . The device of  claim 1 , wherein
 the data block of the second error correction code is recorded in a page having an error-expected value smaller than an average value of error-expected values of pages in a memory chip.   
     
     
       6. A storage device comprising:
 memory chips including a first memory chip, and a second memory chip, each of the first memory chip and the second memory chip having a plurality of blocks and each block including a plurality of pages;   a first encoder which obtains a first error check code and a first error correction code based on an original data, wherein the original data, the first error check code, and the first error correction code are recorded in the first memory chip;   a second encoder which obtains a second error correction code for the original data, wherein the type of the second error correction is different from the type of the first error correction;   a third encoder which obtains a second error check code and a third error correction code based on the second error correction code, wherein the second error correction code, the second error check code, and the third error correction code are recorded in the second memory chip;   a first decoder which decodes the first error correction code recorded in the first memory chip;   a second decoder which decodes the third error correction code recorded in the second memory chip;   a third decoder which performs a first error check of the decoded first error correction code, by using the first error check code;   a fourth decoder which performs a second error check of the decoded third error correction code, by using the second error check code; and   a fifth decoder which decodes the second error correction code of the first memory chip and the second memory chip, based on a first result of a first sum of error number obtained from the first error check and the second error check,   wherein
 if the first result of the first sum is 0, then an error correction processing is completed, and 
 if the first result of the first sum is not 0, then the fifth decoder decodes the second error correction code across the pages of the first and second memory chips and the error correction processing is performed.  
   
     
     
       7. The storage device according to  claim 6 , wherein
 when the first sum of error number is greater than 0 and the smaller than or equal to a predetermined number, the fifth decoder decodes the second error correction code by using an erasure correction to complete the error correction processing.    
     
     
       8. The storage device according to  claim 6 , wherein
 when the first sum of error number exceeds a predetermined number, the fifth decoder decodes the second error correction code by using a normal error correction processing.    
     
     
       9. The storage device according to  claim 8 , wherein
 the first decoder decodes a fourth error correction code and the second decoder decodes a fifth error correction code, the fourth error correction code and the fifth error correction code being latest error codes obtained after the fifth decoder decodes the second error correction code by using normal error correction processing.    
     
     
       10. The storage device according to  claim 9 , wherein
 the third decoder performs a third error check of the fourth correction code and the fourth decoder performs a fourth error check of the fourth correction code.    
     
     
       11. The storage device according to  claim 10 , wherein the fifth decoder decodes the fourth error correction code and the fifth error correction code, based on a second result of a second sum of error number obtained from the third error check by the third decoder and the fourth error check by the fourth decoder.  
     
     
       12. The storage device according to  claim 11 , wherein
 if the second result of the second sum is 0, then an error correction processing is completed, and   is the second result of the second sum is not 0, then the fifth decoder decodes the second error correction code across the pages of the first memory chip and the second memory chip and then the error correction processing is performed.    
     
     
       13. The storage device according to  claim 12 , wherein
 if the second result of the second sum is greater than 0 and smaller than or equal to the predetermined number, the fifth decoder decodes the second error correction code by using an erasure correction to complete the error correction processing.    
     
     
       14. The storage device according to  claim 6 , wherein the second error correction code is obtained by extracting a symbol corresponding to the original data in the first memory chip and the second memory chip.  
     
     
       15. The storage device according to  claim 6 , wherein the decoding the first error correction codes and the decoding the second error correction codes are repeatedly performed.  
     
     
       16. The storage device according to  claim 6 , wherein
 the second error correction code, the second error check code, and the third error correction code are recorded on a second page of the second memory chip, and   the second page has an error-expected value smaller than an average value of error-expected values of the plurality of pages in the first memory chip.    
     
     
       17. The storage device according to  claim 6 , wherein
 the storage device further includes an interface connectable to a host.    
     
     
       18. The storage device according to  claim 6 , wherein
 a first direction of the decoding the first error correction code and a second direction of the decoding the second error correction code are crossing.    
     
     
       19. The storage device according to  claim 7 , wherein
 the first encoder obtains the first error check code of Cyclic Redundancy Check (CRC) code and the first error correction code of a systematic code,   the second encoder obtains the second error correction code of Reed-Solomon (RS) code, and   the third encoder obtains the second error check code of Cyclic Redundancy Check (CRC) code and the third error correction code of a systematic code.    
     
     
       20. The storage device according to  claim 19 , wherein
 the systematic code is Bose-Chaudhuri-Hocquenghem (BCH) code.