Three-dimensional semiconductor device

Abstract

A 3D semiconductor device is provided, comprising plural memory layers vertically stacked on a substrate and parallel to each other; plural selection lines disposed on the memory layers and parallel to each other; plural bit lines disposed on the selection lines, and the bit lines arranged in parallel to each other and in perpendicular to the selection lines; plural strings formed vertically to the memory layers and the selection lines, and the strings electrically connected to the corresponding selection lines; a plurality of cells respectively defined by the strings, the selection lines and the bit lines correspondingly, and the cells arranged in a plurality of rows and columns, wherein a column direction is parallel to the bit lines while a row direction is parallel to the selection lines. The adjacent cells in the same column are electrically connected to the different bit lines.

What is claimed is: 
     
       1. A three-dimensional (3D) semiconductor device, comprising:
 a plurality of memory gate layers vertically stacked on a substrate and parallel to each other; 
 a plurality of selection lines disposed on the memory gate layers and parallel to each other; 
 a plurality of bit lines disposed on the selection lines, and the bit lines arranged in parallel to each other and in perpendicular to the selection lines; 
 a plurality of strings formed vertically to the memory gate layers and the selection lines, and the strings electrically connected to the corresponding selection lines; 
 a plurality of cells respectively defined by the strings, the selection lines and the bit lines correspondingly, and the cells arranged in a plurality of rows and columns, wherein the bit lines are parallel to a column direction while the selection lines are parallel to a row direction; and 
 a plurality of string contacts formed vertically to the gate layers and the selection lines, and each of the string contacts disposed correspondingly at each of the string of the cells, wherein the string contacts are electrically connected to the corresponding selection lines and the corresponding bit lines;  
 wherein the adjacent cells in the same column are electrically connected to the different bit lines; and 
 wherein positions of the string contacts are correspondingly shifted away from centers of the string of the cells. 
 
     
     
       2. The device according to  claim 1 , wherein at least two bit lines are disposed correspondingly to the cells arranged in the same column. 
     
     
       3. The device according to  claim 1 , wherein four bit lines are disposed correspondingly to the cells arranged in the same column. 
     
     
       4. The device according to  claim 1 , wherein the cells of at least two adjacent rows are electrically connected to one of the selection lines. 
     
     
       5. The device according to  claim 1 , wherein the cells of four adjacent rows are electrically connected to one of the selection lines. 
     
     
       6. The device according to  claim 1 , further comprising:
 a plurality of string contacts formed vertically to the memory layers and the selection lines, and each of the string contacts disposed correspondingly at each of the strings of the cells, wherein the string contacts are electrically connected to the corresponding selection lines and the corresponding bit lines.   
     
     
       7. The device according to  claim 6 , wherein positions of the string contacts are correspondingly shifted away from centers of the strings of the cells. 
     
     
       8. The device according to claim  6   1 , wherein the adjacent string contacts of the cells arranged in the same row are misaligned. 
     
     
       9. The device according to claim  6   1 , wherein for the string contacts of the cells arranged in the same row, every other string contact is aligned to form a straight line along the row direction. 
     
     
       10. The device according to  claim 9 , wherein the string contacts of the cells arranged in the same row are aligned at a first straight line and a second straight line along a row direction, and the first straight line is positioned correspondingly to an upper portion of the strings while the second straight line is positioned correspondingly to a lower portion of the strings. 
     
     
       11. The device according to  claim 9 , wherein the string contacts of each row are electrically connected to one of the selection lines. 
     
     
       12. The device according to  claim 9 , wherein the string contacts of every four rows are electrically connected to one of the selection lines. 
     
     
       13. The device according to claim  6   1 , wherein two of the adjacent string contacts of the cells arranged in the same column are misaligned. 
     
     
       14. The device according to claim  6   1 , wherein for the string contacts of the cells arranged in the same column, at least every other string contact is aligned to form a straight line along the column direction. 
     
     
       15. The device according to claim  6   1 , wherein for the string contacts of the cells arranged in the same column, every other three string contacts are contact is aligned to form a straight line along the column direction, and the string contacts of every four rows are electrically connected to one of the selection lines, and each of the bit lines on the cells is positioned correspondingly along each of the straight lines. 
     
     
       16. The device according to claim  6   1 , wherein the string contacts are directly connected to the corresponding bit lines when of the cells are arranged in a honeycomb array, and each of the string contacts is positioned corresponding to a center of each of the cells when the cells are arranged in the honeycomb array, and each of the selection lines corresponds to the cells in two adjacent rows. 
     
     
       17. The device according to claim  6   1 , wherein for the string contacts of the cells in the same column, the string contacts of the cells in every other rows are respectively shifted to a left position and a right position, and the adjacent two bit lines are respectively disposed along the left position and a right position of the cells in the same column, wherein the string contacts are oval or rectangular in shape, and each has a size of X in width parallel to the row direction and Y in length parallel to the column direction, and Y>X, or Y>2X. 
     
     
       18. The device according to claim  6   1 , wherein the string contacts are electrically connected to the corresponding bit lines through a patterned metal layer and a plurality of conductive vias when the cells are arranged in a matrix array. 
     
     
       19. The device according to  claim 18 , wherein the patterned metal layer comprises a plurality of metal portions respectively formed on the corresponding string contacts of the cells, and each of the conductive vias formed on each of the metal portions is electrically connected to the corresponding bit line, the metal portions partially or fully cover the corresponding string contacts, and the adjacent metal portions of the cells in the same row are misaligned, wherein a distance between the two adjacent cells along the row direction is defined as a cell pitch P X  while another distance between the two adjacent cells along the column direction is defined as a cell pitch P y ,
 when one of the metal portions at least partially covers the corresponding string contact of the cell, and said metal portion at least comprises a first part having a rectangular shape and a size of X in width parallel to the row direction and Y1 in length parallel to the column direction, wherein 2P X >X>P X  and Y1<1/2P y ; when one of the metal portions fully covers the corresponding string contact, said metal portion comprises the first part and a second part connected to the first part, and the first and second parts in sum has an overall length Y2 parallel to the column direction, wherein Y2>1/2P y . 
 
     
     
       20. The device according to  claim 1 , wherein each of the strings comprises a channel layer surrounding a conductive layer, and the conductive layers of the cells in the adjacent rows partially overlap when the cells are arranged in a honeycomb array. 
     
     
       21. The device according to  claim 1 , wherein for the string contacts of the cells in the same column, the string contacts of the cells in every other row are respectively shifted to a left position and a right position, and the adjacent two bit lines are respectively disposed along the left position and a right position of the cells in the same column, wherein each of the string contacts has a size of X in width parallel to the row direction and Y in length parallel to the column direction, and Y>X. 
     
     
       22. The device according to  claim 1 , wherein for the string contacts of the cells in the same column, the string contacts of the cells in every other row are respectively shifted to a left position and a right position, and the adjacent two bit lines are respectively disposed along the left position and a right position of the cells in the same column, wherein each of the string contacts has a size of X in width parallel to the row direction and Y in length parallel to the column direction, and Y>2X. 
     
     
       23. A three-dimensional (3D) semiconductor device, comprising:
 a plurality of gate layers vertically stacked on a substrate and parallel to each other to form a memory stack extending along a first direction, the memory stack having a first width across the first direction;   a plurality of selection lines disposed over the memory stack and parallel to each other, the plurality of selection lines including a first selection line above the memory stack and within the first width of the memory stack, and a second selection line above the memory stack and within the first width of the memory stack, the first and second selection lines are disposed laterally apart from each other and located at same horizontal level;   a plurality of bit lines disposed over the first and second selection lines, arranged in parallel to each other and perpendicular to the first and second selection lines;   a plurality of strings formed vertically to the gate layers and the first and second selection lines, and the strings electrically connected to the corresponding first and second selection lines and electrically connected to the gate layers;   a plurality of cells respectively defined by the strings, the first and second selection lines and the bit lines correspondingly, and the cells arranged in a plurality of rows and columns according to the first direction and a second direction, wherein the bit lines are parallel to the second direction while the selection lines are parallel to the first direction; and   a plurality of string contacts formed vertically to the gate layers and the selection lines, and each of the string contacts disposed correspondingly at each of the strings of the cells, wherein the string contacts are electrically connected to the corresponding first selection line, second selection line, and the corresponding bit lines;   wherein adjacent cells in the same column within the first selection line are electrically connected to different bit lines, and adjacent cells in the same column within the second selection line are electrically connected to different bit lines; and   wherein positions of the string contacts are correspondingly shifted away from centers of the strings of the cells.   
     
     
       24. The device according to  claim 23 , wherein there are at least two rows of cells within the first selection line, and at least two rows of cells within the second selection line. 
     
     
       25. The device according to  claim 24 , wherein there are at least two bit lines in the plurality of bit lines overlying each column of cells in the plurality of rows and columns. 
     
     
       26. The device according to  claim 23 , wherein there are four rows of cells within the first selection line. 
     
     
       27. The device according to  claim 23 , wherein at least two bit lines are disposed correspondingly to the cells arranged in the same column. 
     
     
       28. The device according to  claim 23 , wherein the cells of at least two adjacent rows are electrically connected to one of the selection lines. 
     
     
       29. The device according to  claim 23 , wherein for the string contacts of the cells arranged in the same row, every other string contact is aligned to form a straight line along the first direction. 
     
     
       30. The device according to  claim 29 , wherein the string contacts of every four rows are electrically connected to one of the first selection line or the second selection line. 
     
     
       31. The device according to  claim 23 , wherein two of the adjacent string contacts of the cells arranged in the same column are misaligned. 
     
     
       32. The device according to  claim 23 , wherein for the string contacts of the cells in the same column, the string contacts of the cells in every other rows are respectively shifted to a left position and a right position, and the adjacent two bit lines are respectively disposed along the left position and a right position of the cells in the same column, wherein the string contacts are oval or rectangular in shape, and each has a size of X in width parallel to the first direction and Y in length parallel to the second direction, and Y>2X. 
     
     
       33. The device according to  claim 23 , wherein for the string contacts of the cells in the same column, the string contacts of the cells in every other rows are respectively shifted to a left position and a right position, and the adjacent two bit lines are respectively disposed along the left position and a right position of the cells in the same column, and each string contact has a size of X in width parallel to the first direction and Y in length parallel to the second direction, and Y>2X. 
     
     
       34. The device according to  claim 23 , wherein each of the strings comprises a storage layer surrounding a conductive layer, and the conductive layers of the cells in the adjacent rows partially overlap when the cells are arranged in a honeycomb array. 
     
     
       35. The device according to  claim 23 , wherein the cells in the adjacent rows partially overlap when the cells are arranged in a honeycomb array.