Semiconductor memory device

Abstract

A CRC code is generated from an original data, a BCH code is generated with respect to the original data and the CRC code, and the original data, the CRC code, and the BCH code are recorded in pages selected from different planes of a plurality of memory chips. An RS code is generated from the original data across pages, a CRC code is generated with respect to the RS code, a BCH code is generated with respect to the RS code and the CRC code, and the RS code, the CRC code, the BCH code are recorded in a memory chip different from a memory chip including the original data. When reading data, error correction is performed on the original data by using the BCH code, and then CRC is calculated. If the number of errors is the number of errors that is correctable by erasure correction using the RS code, the original data is corrected by the erasure correction. If the number of errors exceeds an erasure correction capability of the RS code, normal error correction using the RS code is performed, and further error correction using the BCH code is performed.

What is claimed is: 
     
       1. A semiconductor memory device comprising:
 a memory chip;   a first encoder/decoder (E/D) configured to obtain a first error check code and a first error correction code based on an original data, the original data, the first error check code, and the first error correction code are recorded on a first page of a memory chip;   an encoder configured to obtain a second error correction code for the original data, the type of the second error correction is different from the type of the first error correction; and   a second E/D configured to obtain a second error check code and a third error correction code based on the second error correction code wherein, the second error correction code, the second error check code, and the third error correction code are recorded on a second page of a memory chip.   
     
     
       2. The device of  claim 1 , wherein
 the first E/D obtains the first error check code based on the original data and obtains the first error correction code based on the original data and the first error check code, and the second E/D obtains the second error check code based on the second error correction code and obtains the third error correction code based on the second error correction code and the second error check code.   
     
     
       3. The device of  claim 2 , wherein
 a size of a data block of the original data and a size of a data block of the second error correction code are the same.   
     
     
       4. The device of  claim 3 , wherein
 the second error correction code is formed across a plurality of pages in a direction crossing data blocks of the original data.   
     
     
       5. The device of  claim 1 , wherein
 the data block of the second error correction code is recorded in a page having an error-expected value smaller than an average value of error-expected values of pages in a memory chip.   
     
     
       6. A memory device comprising:
 a plurality of memory chips, each chip having a plurality of pages;   a first encoder which obtains a first error check code and a first error correction code based on an original data, wherein the original data, the first error check code, and the first error correction code are recorded on a first page of a first memory chip;   a second encoder which obtains a second error correction code for the original data, wherein the type of the second error correction is different from the type of the first error correction;   a third encoder which obtains a second error check code and a third error correction code based on the second error correction code wherein the second error correction code, the second error check code, and the third error correction code are recorded on a second page of a second memory chip;   a first decoder which decodes the first error correction code recorded on the first page of the first memory chip and performs an error correction for the original data and the first error check code;   a second decoder which decodes the third error correction code recorded on the second page of the second memory chip and performs an error correction for the second error check code and the second error correction code;   a third decoder which decodes the first error check code and performs a first error check on a decoding result by the first decoder;   a fourth decoder which decodes the second error check code and performs a second error check on a decoding result by the second decoder; and   a fifth decoder which decodes the second error correction code across the pages of the plurality of the memory chips, based on a result that is a sum of error number obtained from the error check by the third decoder and the fourth decoder,   wherein the decoding the first error correction codes and the decoding the second error correction codes are repeatedly performed.    
     
     
       7. The device of  claim 6 , wherein
 the first encoder obtains the first error check code based on the original data and obtains the first error correction code based on the original data and the first error check code, and the third encoder obtains the second error check code based on the second error correction code and obtains the third error correction code based on the second error correction code and the second error check code.    
     
     
       8. The device of  claim 7 , wherein
 a size of a data block of the original data and a size of a data block of the second error correction code are the same.    
     
     
       9. The device of  claim 8 , wherein
 the second error correction code is formed across a plurality of pages in a direction crossing data blocks of the original data.    
     
     
       10. The device of  claim 6 , wherein
 a data block of the second error correction code is recorded in the second page of the second memory chip in which an error-expected value is smaller than an average value of error-expected values of pages in the second memory chip.    
     
     
       11. The device of  claim 6 , wherein
 based on the first error check and the second error check by the third decoder and the fourth decoder,   (i) when the sum of the number of errors is 0 as the result of the error check, an error correction processing is completed,   (ii) when the sum of the number of errors is not 0 as the result of the error check, the fifth decoder decodes the second error correction code,   wherein (a) in a case when the sum of the number of errors is greater than 0 and smaller than or equal to a predetermined number defined by a configuration of the second correction code, the fifth decoder decodes the second correction code by using an erasure correction, and the error correction processing is completed, and (b) in a case when the sum of the number of errors exceeds the predetermined number, the fifth decoder decodes the second correction code by using a normal error correction processing.    
     
     
       12. The device of  claim 6 , the device further includes an interface connectable to a host.  
     
     
       13. The device of  claim 6 , wherein a first direction of the decoding the first error correction code and a second direction of the decoding the second error correction code are crossing.