Isolation region fabrication for replacement gate processing

Abstract

A semiconductor structure includes a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a bottom silicon layer, a buried oxide (BOX) layer, and a top silicon layer; a plurality of active devices formed on the top silicon layer; and an isolation region located between two of the active devices, wherein at least two of the plurality of active devices are electrically isolated from each other by the isolation region, and wherein the isolation region extends through the top silicon layer to the BOX layer.

The invention claimed is: 
     
       1. A semiconductor structure, comprising:
 a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a bottom silicon layer, a buried oxide (BOX) layer, and a top silicon layer;   a plurality of active devices formed on the top silicon layer; and   an isolation region located between two of the plurality of active devices, wherein at least two of the plurality of active devices are electrically isolated from each other by the isolation region, wherein the isolation region extends through the top silicon layer to the BOX layer, wherein the isolation region further extends between a pair of spacers that are located on the top silicon layer on either side of the isolation region, and wherein the isolation region further extends through an interlevel dielectric (ILD) layer that is located over the pair of spacers.   
     
     
       2. The semiconductor structure of  claim 1 , further comprising a hardmask layer located over the isolation region. 
     
     
       3. The semiconductor structure of  claim 2 , wherein the hardmask layer comprises silicon nitride. 
     
     
       4. A semiconductor device comprising:
 a substrate including a top silicon layer that includes a fin;   a first gate structure disposed on the fin;   a second gate structure disposed on the fin;   an isolation region disposed between the first gate structure and the second gate structure, and electrically isolating the first gate structure from the second gate structure;   a first region disposed on a first side of the isolation region and disposed on the substrate;   a second region disposed on a second side of the isolation region and disposed on the substrate;   a third region including an interlevel dielectric (ILD) layer and including a first portion disposed on the first region and a second portion disposed on the second region; and   a silicon nitride layer disposed on the first region and the second region,   wherein the isolation region extends between the first region and the second region, and extends through the third region,   the isolation region extends from above a top of the fin to a bottom of the fin,   the fin extends in a first horizontal direction and at least the first gate structure extends in a second horizontal direction perpendicular to the first horizontal direction, and   wherein a top surface of the first gate structure is at substantially the same level as a top surface of the isolation region.   
     
     
       5. The semiconductor device of  claim 4 , wherein the third region includes a third portion disposed on the first gate structure and a fourth portion disposed on the second gate structure. 
     
     
       6. The semiconductor device of  claim 4 , wherein the silicon nitride layer is disposed on the isolation region. 
     
     
       7. The semiconductor device of  claim 4 , wherein the silicon nitride layer is disposed on the third region. 
     
     
       8. The semiconductor device of  claim 4 , wherein the isolation region extends through the third region in a direction that is substantially parallel with respect to a top surface of the substrate. 
     
     
       9. The semiconductor device of  claim 4 , wherein the isolation region extends through the third region in a direction that is substantially perpendicular with respect to a top surface of the substrate. 
     
     
       10. The semiconductor device of  claim 4 , wherein the third region is disposed on a sidewall of the first region and on a sidewall of the second region. 
     
     
       11. The semiconductor device of  claim 4 , wherein the third region is disposed on a top surface of the first region and on a top surface of the second region. 
     
     
       12. The semiconductor device of  claim 4 , wherein the isolation region contacts the third region. 
     
     
       13. The semiconductor device of  claim 4 , wherein the isolation region contacts the silicon nitride layer. 
     
     
       14. A semiconductor device comprising:
 a substrate including a top silicon layer that includes a fin;   a first gate structure disposed on the fin;   a second gate structure disposed on the fin;   an isolation region disposed between the first gate structure and the second gate structure, and electrically isolating the first gate structure from the second gate structure;   a first region disposed on a first side of the isolation region and disposed on the substrate;   a second region disposed on a second side of the isolation region and disposed on the substrate;   a third region including a first portion disposed on the first region and a second portion disposed on the second region;   a silicon nitride layer disposed on the first region and the second region, disposed on the isolation region above the isolation region to vertically overlap the isolation region, and disposed adjacent to the third region;   a first channel disposed below the first gate structure; and   a second channel disposed below the second gate structure,   wherein the isolation region extends between the first region and the second region, and extends through the third region that is disposed on the first region and the second region.