Array substrate and manufacturing method thereof, display panel and display device

Abstract

An array substrate and a manufacturing method thereof, a display panel and display device relating to display technology are provided. The array substrate includes: a substrate; a light shielding layer being of electrical conductive over the substrate; a buffer layer over the light shielding layer; an active layer insulated from the light shielding layer by the buffer layer and shielded by the light shielding layer against light radiation; a gate insulating layer disposed over the active layer; and a patterned first electrode layer having a first electrode over the gate insulating layer, the first electrode being a gate electrode; wherein the patterned first electrode layer further comprises a second electrode over the buffer layer, the second electrode having at least a portion in contact with the buffer layer. The buffer layer comprises a first via-hole, and the second electrode is in electrical connection with the light shielding layer through the first via-hole.

What is claimed is: 
     
       1. An array substrate comprising:
 a substrate; 
 a light shielding layer being of electrical conductive over the substrate; 
 a buffer layer over the light shielding layer; 
 an active layer insulated from the light shielding layer by the buffer layer and shielded by the light shielding layer against light radiation; 
 a gate insulating layer disposed over the active layer; 
 a gate line in a same layer with the light shielding layer; and 
 a patterned first electrode layer having a first electrode over the gate insulating layer, the first electrode being a gate electrode; wherein the patterned first electrode layer further comprises a second electrode over the buffer layer, the second electrode having at least a portion in contact with the buffer layer, 
 wherein the buffer layer comprises a first via-hole, and the second electrode is in electrical connection with the light shielding layer through the first via-hole. 
 
     
     
       2. The array substrate as claimed in  claim 1 , wherein the buffer layer further comprises a second via-hole, and the gate line is in electrical connection with the gate electrode through the second via-hole. 
     
     
       3. The array substrate as claimed in  claim 1 , wherein the second electrode is a source electrode. 
     
     
       4. The array substrate as claimed in  claim 3 , wherein the patterned first electrode layer further comprises a third electrode which is a drain electrode. 
     
     
       5. The array substrate as claimed in  claim 2 , wherein the array substrate further comprises a passivation layer and a second electrode layer overthe patterned first electrode layer;
 the passivation layer comprises a third via-hole adjacent to the second via-hole, and a fourth via-hole through which the second electrode layer is connected to the gate electrode; and 
 the second electrode layer is connected to the gate line through the second via-hole and the third via-hole. 
 
     
     
       6. The array substrate as claimed in  claim 5 , wherein the second electrode layer comprises a transparent electrode, the transparent conductive electrode comprising one or a combination selected from a group consisting of: a pixel electrode, a common electrode and an anode. 
     
     
       7. The array substrate as claimed in  claim 5 , further comprising a first connecting electrode connected to the gate line through the second via-hole, and a second connecting electrode connected to the first connecting electrode through the third via-hole and connected to the gate electrode through the fourth via-hole. 
     
     
       8. The array substrate as claimed in  claim 1 , wherein the active layer includes a first portion in contact with the second electrode, the first portion being treated to be conductive. 
     
     
       9. The array substrate as claimed in  claim 8 , wherein the active layer further includes a second portion not covered by the gate insulating layer or the second electrode, the second portion being treated to be conductive. 
     
     
       10. The array substrate as claimed in  claim 1 , wherein the active layer comprises at least one or a combination of materials selected from a group consisting of: indium gallium zinc oxide, indium zinc oxide, zinc oxide and gallium oxide zinc. 
     
     
       11. A display panel, wherein the display panel comprises the array substrate as claimed in  claim 1 . 
     
     
       12. A method of manufacturing an array substrate comprising:
 forming a light shielding layer of electrical conductive material over a substrate; 
 forming a buffer layer over the substrate having the light shielding layer formed thereon; 
 forming an active layer and a gate insulating layer sequentially over the buffer layer, the active layer being insulated from the light shielding layer by the buffer layer and shielded by the light shielding layer against light radiation; 
 forming a gate line in a same layer with the light shielding layer; and 
 forming a patterned first electrode layer having a first electrode over the gate insulating layer, the first electrode being a gate electrode; wherein the patterned first electrode layer further comprises a second electrode over the buffer layer, the second electrode having at least a portion in contact with the buffer layer; 
 wherein the buffer layer comprises a first via-hole, the second electrode is in electrical connection with the light shielding layer through the first via-hole. 
 
     
     
       13. The method as claimed in  claim 12 , wherein the buffer layer further comprises a second via-hole, and the gate line is in electrical connection with the gate electrode through the second via-hole. 
     
     
       14. A method of manufacturing an array substrate comprising:
 forming a light shielding layer of electrical conductive material over a substrate; 
 forming a buffer layer over the substrate having the light shielding layer formed thereon; 
 forming an active layer and a gate insulating layer sequentially over the buffer layer, the active layer being insulated from the light shielding layer by the buffer layer and shielded by the light shielding layer against light radiation; and 
 forming a patterned first electrode layer having a first electrode over the gate insulating layer, the first electrode being a gate electrode; wherein the patterned first electrode layer further comprises a second electrode over the buffer layer, the second electrode having at least a portion in contact with the buffer layer; 
 wherein the buffer layer comprises a first via-hole, the second electrode is in electrical connection with the light shielding layer through the first via-hole; 
 wherein the step offorming of forming the active layer and the gate insulating layer comprises: 
 sequentially forming a semiconductor film and a gate insulating film, and forming a photoresist on the gate insulating film; 
 subjecting the photoresist to exposure using a half tone mask, thereby forming a photoresist fully-reserved portion, a photoresist half-reserved portion and a photoresist fully-removed portion after development; 
 wherein the photoresist fully-reserved portion corresponding corresponds to the gate insulating layer to be formed, the photoresist half-reserved portion corresponding corresponds to a portion of the active layer to be formed that is not covered by the gate insulating layer; the photoresist fully-removed portion corresponding corresponds to other portions; 
 etching the gate insulating film and the semiconductor film that are correspond to the photoresist fully-removed portion by dry etching and wet etching process; 
 removing the photoresist half-reserved portion by ashing process; 
 etching the exposed gate insulating film by dry etching process to form the gate insulating layer; and 
 treating the portion of active layerthat layer that is not covered by the gate insulating layer to be conductive with plasma. 
 
     
     
       15. The method as claimed in  claim 12 , whereinthe step of forming the patterned first electrode layer comprises:
 forming a metal conductive film on the substrate having the active layer and the gate insulating layer formed thereon; 
 forming a photoresist layer, wherein etching selectivity ratio of the metal conductive film to the active layer is greater than or equal to 10:1; 
 subjecting the photoresist layer to exposure using a mask, thereby forming a photoresist fully-reserved portion and a photoresist fully-removed portion after development; and 
 etching the metal conductive film by wet etching process to form the patterned first electrode layer. 
 
     
     
       16. The method as claimed in  claim 15 , wherein prior to the forming of the patterned first electrode layer, the orthographic projection of the gate electrode to be formed on the substrate is completely covered by the orthographic projection of the gate insulating layer on the substrate, and the size of the gate insulating layer is greater than that of the gate electrode to be formed;
 wherein the method further comprises etching the gate insulating layer by dry etching process after etching the metal conductive film by wet etching process and before removing the photoresist fully-reserved portion. 
 
     
     
       17. The method as claimed in  claim 16 , whereinetching of the gate insulating layer exposes a second portion of the active layer;
 wherein the method further comprises treating the second portion of the active layer to be conductive with plasma. 
 
     
     
       18. The method as claimed in  claim 13 , whereinthe first via-hole and the second via-hole are formed by dry etching process. 
     
     
       19. The array substrate as claimed in  claim 1 , wherein the patterned first electrode layer further comprises a third electrode which is a drain electrode, the second electrode is a source electrode;
 the active layer includes a first portion in contact with the second electrode, the first portion being treated to be conductive; and   the active layer further includes a second portion not covered by the gate insulating layer and/or the second electrode, the second portion being treated to be conductive.    
     
     
       20. The array substrate as claimed in  claim 1 , wherein the buffer layer further comprises a second via-hole, and the gate line is in electrical connection with the patterned first electrode layer through the second via-hole;
 the array substrate further comprises a passivation layer and a second electrode layer over the patterned first electrode layer;   the passivation layer comprises a fourth via-hole through which the second electrode layer is connected to the patterned first electrode layer; and   the gate line and the light shielding layer have a same material.