Non-volatile semiconductor memory device including application of different voltages to memory cells based on their proximity to a selected memory cell

Abstract

A non-volatile semiconductor memory device has a NAND string, in which multiple memory cells are connected in series. A read procedure is performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a selected voltage while unselected memory cells are driven to be turned on without regard to cell data thereof. In the read procedure, a first read pass voltage is applied to unselected memory cells except an adjacent and unselected memory cell disposed adjacent to the selected memory cell, the adjacent and unselected memory cell being completed in data write later than the selected memory cell, and a second read pass voltage higher than the first read pass voltage is applied to the adjacent and unselected memory cell.

What is claimed is: 
     
       1. A method for controlling a non-volatile semiconductor memory device having a NAND string, in which multiple memory cells are connected in series, comprising:
 a read procedure performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a selected voltage while unselected memory cells are driven to be turned on without regard to cell data thereof, wherein   a first read pass voltage and a second read pass voltage higher than the first read pass voltage are generated by a voltage generation circuit, and wherein   the first read pass voltage generated by the voltage generation circuit is applied to unselected memory cells except adjacent and unselected memory cells disposed adjacent to the selected memory cell, and the second read pass voltage generated by the voltage generation circuit is applied to at least one of the adjacent and unselected memory cells in the read procedure.   
     
     
       2. The method according to  claim 1 , wherein
 the second read pass voltage is applied to the adjacent and unselected memory cell being completed in data write later than the selected memory cell.   
     
     
       3. The method according to  claim 1 , wherein
 the read procedure is a normal read procedure for reading data of the selected memory cell after data writing.   
     
     
       4. The method according to  claim 1 , wherein
 the read procedure is a write-verify read procedure for verify-reading data of the selected memory cell in a data write mode.   
     
     
       5. The method according to  claim 3 , wherein
 in the normal read procedure, the second read pass voltage is applied to one cell in two adjacent and unselected memory cells disposed adjacent to the selected memory cell, the one cell having been written previously to the selected memory cell; and a third pass voltage is applied to the other cell in the two adjacent and unselected memory cells, the other cell having been written later than the selected memory cell, the third read pass voltage being selected in level in accordance with the cell's threshold shift amount.   
     
     
       6. The method according to  claim 5 , wherein
 the third read pass voltage is set to be lower than the first read pass voltage in case the cell's threshold shift amount is less than a certain level while the third read pass voltage is set to be equal to the second read pass voltage in case the cell's threshold shift amount is greater than the certain level.   
     
     
       7. The method according to  claim 5 , wherein
 the normal read procedure includes:   a first read operation performed for reading data of the other cell previously to reading data of the selected memory cell when it is selected; and   a second read operation performed for reading data of the selected memory cell on the condition that the third read pass voltage is selected in level with reference to the read data of the first read operation.   
     
     
       8. The method according to  claim 1 , wherein
 the memory cell stores four-level data defined by data level E, A, B and C (where, E<A<B<C), data level E being defined as an erase state with a negative cell threshold while data levels A, B and C are defined as write states with positive cell threshold voltages, and   a data write procedure includes: a lower page write mode for selectively writing the memory cells with data level E to have a medium level LM set between data level A and B; and an upper page write mode for selectively writing the memory cells with data level E and data level LM to have data level A and data level B or C, respectively, and   in the data write procedure, the memory cells in the NAND string are selected from a source line side in such an order that a first memory cell is written in a lower page write mode; a second memory cell adjacent to the first memory cell disposed adjacent to the first memory cell on a bit line side is written in the successive lower page write mode; and then the first memory cell is written in an upper page write mode.   
     
     
       9. A method for controlling a non-volatile semiconductor memory device having a NAND string, in which multiple memory cells are connected in series, comprising:
 a write-verifying procedure performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a write-verifying voltage and unselected memory cells are driven to be turned on without regard to cell data thereof; and   a normal read procedure performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a read voltage and unselected memory cells are driven to be turned on without regard to cell data thereof, wherein   in the write-verifying procedure, a first read pass voltage is applied to unselected memory cells except two adjacent and unselected memory cells disposed adjacent to the selected memory cell; a second read pass voltage higher than the first read pass voltage is applied to one cell of the two adjacent and unselected memory cells, the one cell having been written previously to the selected memory cell; and a third read pass voltage lower than the first read pass voltage is applied to the other cell, which is written later than the selected memory cell, and   in the normal read procedure, the first read pass voltage is applied to the unselected memory cells except the two adjacent and unselected memory cells; the second read pass voltage higher than the first read pass voltage is applied to one cell of the two adjacent and unselected memory cells, the one cell having been written previously to the selected memory cell; and a fourth read pass voltage is applied to the other cell, which has been written later than the selected memory cell, the fourth read pass voltage being selected in level in accordance with the cell's threshold shift amount.   
     
     
       10. The method according to  claim 9 , wherein
 the fourth read pass voltage is set to be lower than the first read pass voltage in case the cell's threshold shift amount is less than a certain level while the fourth read pass voltage is set to be equal to the second read pass voltage in case the cell's threshold shift amount is greater than the certain level.   
     
     
       11. The method according to  claim 10 , wherein
 the normal read procedure includes:   a first read operation performed for reading data of the other cell previously to reading data of the selected memory cell when it is selected; and   a second read operation performed for reading data of the selected memory cell on the condition that the fourth read pass voltage is selected in level with reference to the read data of the first read operation.   
     
     
       12. The method according to  claim 9 , wherein
 the memory cell stores four-level data defined by data level E, A, B and C (where, E<A<B<C), data level E being defined as an erase state with a negative cell threshold while data levels A, B and C are defined as write states with positive cell threshold voltages, and   a data write procedure includes: a lower page write mode for selectively writing the memory cells with data level E to have a medium level LM set between data level A and B; and an upper page write mode for selectively writing the memory cells with data level E and data level LM to have data level A and data level B or C, respectively, and   in the data write procedure, the memory cells in the NAND string are selected from a source line side in such an order that a first memory cell is written in a lower page write mode; a second memory cell adjacent to the first memory cell disposed adjacent to the first memory cell on a bit line side is written in a successive lower page write mode; and then the first memory cell is written in an upper page write mode.   
     
     
       13. A method for controlling a non-volatile semiconductor memory device having a NAND string, in which multiple memory cells are connected in series, comprising:
 a write-verifying procedure performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a write-verifying voltage and unselected memory cells are driven to be turned on without regard to cell data thereof; and   a normal read procedure performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a read voltage and unselected memory cells are driven to be turned on without regard to cell data thereof, wherein   in the write-verifying procedure, a first read pass voltage is applied to unselected memory cells except adjacent and unselected memory cells adjacent to the selected memory cell; a second read pass voltage lower than the first read pass voltage is applied to one of the adjacent and unselected memory cells, which is written later than the selected memory cell, and   in the normal read procedure, the first read pass voltage is applied to the unselected memory cells except the adjacent and unselected memory cells disposed adjacent to the selected memory cell; a third read pass voltage is applied to one of the adjacent and unselected memory cells, which has been written later than the selected memory cell, the third read voltage being selected in level in accordance with the cell's threshold shift amount, the maximum vale of which is higher than the first read pass voltage.   
     
     
       14. The method according to  claim 13 , wherein
 the memory cell stores four-level data defined by data level E, A, B and C (where, E<A<B<C), data level E being defined as an erase state with a negative cell threshold while data levels A, B and C are defined as write states with positive cell threshold voltages, and   a data write procedure includes: a lower page write mode for selectively writing the memory cells with data level E to have a medium level LM set between data level A and B; and an upper page write mode for selectively writing the memory cells with data level E and data level LM to have data level A and data level B or C, respectively, and   in the data write procedure, the memory cells in the NAND string are selected from a source line side in such an order that a first memory cell is written in a lower page write mode; a second memory cell adjacent to the first memory cell disposed adjacent to the first memory cell on a bit line side is written in a successive lower page write mode; and then the first memory cell is written in an upper page write mode.   
     
     
       15. A method for controlling a non-volatile semiconductor memory device having a NAND string, in which multiple memory cells are connected in series, comprising:
 a write-verifying procedure performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a write-verifying voltage and unselected memory cells are driven to be turned on without regard to cell data thereof; and   a normal read procedure performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a read voltage and unselected memory cells are driven to be turned on without regard to cell data thereof, wherein   in the write-verifying procedure, a first read pass voltage is applied to unselected memory cells except adjacent and unselected memory cells adjacent to the selected memory cell; a second read pass voltage lower than the first read pass voltage is applied to one of the adjacent and unselected memory cells, which is written later than the selected memory cell, and   in the normal read procedure, the first read pass voltage is applied to the unselected memory cells except the adjacent and unselected memory cells disposed adjacent to the selected memory cell; a third read pass voltage is applied to one of the adjacent and unselected memory cells, which has been written later than the selected memory cell, the third read voltage being selected in level in accordance with the cell data, the maximum value of which is higher than the first read pass voltage.   
     
     
       16. The method according to  claim 15 , wherein
 the memory cell stores multi-level data defined as a cell threshold voltage, and   in a data write procedure, the memory cells in the NAND strings are selected in order from a source line side, and the multi-level data writing are completed for each selected memory cell.   
     
     
       17. A non-volatile semiconductor memory device comprising:
 a plurality of NAND strings each comprising a plurality of memory cells connected in series, wherein the NAND strings are coupled to word lines and bit lines;   a plurality of page buffer circuits configured to read data of the bit lines in a read procedure; and   a high voltage generation circuit configured to generate a first read voltage and a second read voltage supplied to the word lines, wherein   the second read voltage is set to be higher than the first read voltage; and   the first read voltage is applied to at least two of first unselected word lines except second unselected word lines disposed adjacent to a selected word line, and the second read voltage is applied to the second unselected word lines in the read procedure; and   the first and second read voltages are sufficient to turn on unselected memory cells in the NAND string without regard to data of the unselected memory cells.   
     
     
       18. The non-volatile semiconductor memory device of  claim 17 , wherein each of the page buffer circuits is coupled to at least two of the bit lines. 
     
     
       19. The non-volatile semiconductor memory device of  claim 17 , wherein the first read voltage and the second read voltage are predetermined to be equal to or more than 4.5V in the read procedure. 
     
     
       20. The non-volatile semiconductor memory device of  claim 17 , wherein the first read voltage is set to be higher than the second read voltage by equal to or more than about 0.6V. 
     
     
       21. The non-volatile semiconductor memory device of  claim 17 , wherein the first read voltage is set to be higher than the second read voltage by equal to or more than 0.3V. 
     
     
       22. The non-volatile semiconductor memory device of  claim 17 , wherein:
 the high voltage generation circuit includes at least one voltage boost circuit; and   the voltage boost circuit is configured to boost a voltage necessary for the read procedure and output the first read voltage or the second read voltage.   
     
     
       23. The non-volatile semiconductor memory device of  claim 17 , wherein:
 the memory device stores single-bit data; and   a difference between the first read voltage and the second read voltage is directed to be a predetermined voltage level without regard to the data stored by the memory cells.   
     
     
       24. The non-volatile semiconductor memory device of  claim 17 , wherein the second read voltage is set to be higher than the first read voltage by a fixed voltage amount based on a capacitive coupling relationship among a selected memory cell having the selected word line and the unselected memory cells adjacent to the selected memory cell. 
     
     
       25. A non-volatile semiconductor memory device comprising:
 a plurality of NAND strings each comprising a plurality of memory cells connected in series, wherein the NAND strings are coupled to word lines and bit lines;   a plurality of page buffer circuits configured to read data of the bit lines in a read procedure; and   a high voltage generation circuit configured to generate a first read voltage, a second read voltage and a third read voltage supplied to the word lines, wherein   the first and second read voltages are set to be higher than the third read voltage;   the second and third read voltages are different from each other;   the second read voltage is higher than the first read voltage;   the first read voltage is applied to at least two of first unselected word lines except second unselected word lines disposed adjacent to a selected word line, and the second and third read voltages are respectively applied to the second unselected word lines in the read procedure; and   the first, second and third read voltages are sufficient to turn on unselected memory cells in the NAND string without regard to data of the unselected memory cells.   
     
     
       26. The non-volatile semiconductor memory device of  claim 25 , wherein the memory cells have dimensions according to a design rule of 56 nm or less. 
     
     
       27. A non-volatile semiconductor memory device comprising:
 a plurality of NAND strings each comprising a plurality of memory cells connected in series, wherein the NAND strings are coupled to word lines and bit lines;   a plurality of page buffer circuits configured to read data of the bit lines in a read procedure; and   a high voltage generation circuit configured to generate a first read voltage and a second read voltage supplied to the word lines, wherein   the memory cells comprise first, second, third and fourth successively higher memory levels having respective first, second, third and fourth threshold voltage distributions,   a first memory cell corresponding to at least one of unselected word lines is written to the fourth memory level,   a selected memory cell in a first NAND string is applied with a select voltage in the read procedure.   the second read voltage is applied to a first unselected memory cell immediately adjacent to the selected memory cell in the first NAND string in the read procedure,   the first read voltage is applied to second unselected memory cells not immediately adjacent to the selected memory cell in the first NAND string in the read procedure, and   the second read voltage is set to be higher than the first read voltage by an amount based upon a desired read margin between the second read voltage and an upper limit of the fourth threshold distribution of the first memory cell.   
     
     
       28. The non-volatile semiconductor memory device of  claim 27 , wherein the memory cells have dimensions according to a design rule of 56 nm or less. 
     
     
       29. The non-volatile semiconductor memory device of  claim 27 , wherein the second read voltage is applied to a second memory cell immediately adjacent to the selected memory cell in the first NAND string in the read procedure. 
     
     
       30. A non-volatile semiconductor memory device comprising:
 a plurality of NAND strings each comprising a plurality of memory cells connected in series and formed in a surface of a semiconductor portion;   word lines respectively connected to each of the memory cells in each NAND string;   a first selection transistor respectively connected to a first end of each of the NAND strings;   a second selection transistor respectively connected to a second end of each of the NAND strings;   a bit line respectively connected to each of the first selection transistors;   a source line connected to each of the second selection transistors;   a first selection line connected to each first selection transistor;   a second selection line connected to each second selection transistor;   a plurality of page buffer circuits configured to read data of the bit lines in a read procedure; and   a high voltage generation circuit configured to generate a first read voltage and a second read voltage supplied to the word lines, wherein   the second selection transistor is connected to a select gate having a first gate length in a direction perpendicular to a channel direction;   each of the word lines has a second gate length in the direction smaller than the first gate length;   each of the word lines comprises a first layer of conductive material having a dimension in a direction perpendicular to the surface of the semiconductor portion;   each of the gates of the second selection transistors comprises a second layer of conductive material having the dimension in the direction perpendicular to the surface of the semiconductor portion;   the second read voltage is set to be higher than the first read voltage;   the second read voltage is set to be higher than the first read voltage;   the first read voltage is applied to at least two of first unselected word lines except second unselected word lines disposed adjacent to a selected word line, and the second read voltage is applied to the second unselected word lines in the read procedure; and   the first and second read voltages are sufficient to turn on unselected memory cells in the NAND string without regard to data of the unselected memory cells.   
     
     
       31. The non-volatile semiconductor memory device of  claim 30 , wherein the first read voltage is set to be higher than the second read voltage by equal to or more than about 0.6V. 
     
     
       32. The non-volatile semiconductor memory device of  claim 30 , wherein the first read voltage is set to be higher than the second read voltage by equal to or more than 0.3V. 
     
     
       33. The non-volatile semiconductor memory device of  claim 30 , wherein the memory cells have dimensions according to a design rule of 56 nm or less. 
     
     
       34. A non-volatile semiconductor memory device comprising:
 a plurality of NAND strings each comprising a plurality of memory cells connected in series, wherein the NAND strings are coupled to word lines and bit lines;   a plurality of page buffer circuits configured to read data of the bit lines in a read procedure; and   a high voltage generation circuit configured to generate a first read voltage and a second read voltage supplied to the word lines, wherein   the second read voltage is set to be higher than the first read voltage;   the first read voltage is applied to at least two of first unselected word lines except second unselected word lines disposed adjacent to a selected word line, and the second read voltage is applied to the second unselected word lines in the read procedure;   the first and second read voltages are sufficient to turn on unselected memory cells in the NAND string without regard to data of the unselected memory cells, and   the memory cells have dimensions according to a design rule of 56 nm or less.   
     
     
       35. The non-volatile semiconductor memory device of  claim 34 , wherein the first read voltage is set to be higher than the second read voltage by equal to or more than about 0.6V. 
     
     
       36. The non-volatile semiconductor memory device of  claim 34 , wherein the first read voltage is set to be higher than the second read voltage by equal to or more than 0.3V. 
     
     
       37. The non-volatile memory device of  claim 17 , wherein the second read voltage is applied to memory cells, of the plurality of memory cells, coupled to the second unselected word lines disposed adjacent to the selected word line being completed in data write later than one of the memory cells, of the plurality of memory cells, coupled to the selected word line.