Memory system having high data transfer efficiency and host controller

Abstract

According to one embodiment, the host controller includes a register set to issue command, and a direct memory access (DMA) unit and accesses a system memory and a device. First, second, third and fourth descriptors are stored in the system memory. The first descriptor includes a set of a plurality of pointers indicating a plurality of second descriptors. Each of the second descriptors comprises the third descriptor and fourth descriptor. The third descriptor includes a command number, etc. The fourth descriptor includes information indicating addresses and sizes of a plurality of data arranged in the system memory. The DMA unit sets, in the register set, the contents of the third descriptor forming the second descriptor, from the head of the first descriptor as a start point, and transfers data between the system memory and the host controller in accordance with the contents of the fourth descriptor.

What is claimed is: 
     
       1. A host controller which is connected to a memory device through an interface, accesses a system memory, and is controlled by a CPU executing a host driver, wherein each of first, third, and fourth descriptors has an attribute field for identifying a type of the descriptors, and designating a processing method of the descriptors, the host controller comprising:
 a register set which is configured to store a part of information in the third descriptor;   a command controller which is configured to issue a command to the memory device according to the information stored in the register set; and   a direct memory access (DMA) unit which is configured to load the first, third, and fourth descriptors into the host controller, and is configured to transfer data between the system memory and the memory device according to the first, third, and fourth descriptors,   wherein the first descriptor includes a plurality of pointers with attributes,   each of the pointers of the first descriptor indicates a leading region of the third descriptor,   the third descriptor includes command issue information and attributes,   the fourth descriptor includes a number of DMA execution information and attributes,   wherein the DMA unit is configured (1) to load the first descriptor, (2) to acquire the pointer from the loaded first descriptor, (3) to load the third descriptor and the fourth descriptor based on the acquired pointer, (4) to execute a data transfer between the system memory and the memory device, (5) to repeat the process of (2) to (4) until the attribute of the first descriptor indicates the end of descriptor, and (6) to generate an interrupt to the CPU when the data transfer is end or during a DMA data transfer,   wherein the third descriptors includes information to generate a data transfer command of the memory device, a command argument, a command number, a block length, and the number of blocks,   wherein the fourth descriptor includes information to designate system memory areas addresses, and sizes for each of a plurality of scattered data in the system memory, and   wherein the DMA unit includes:   a system address controller configured to control addresses of the system memory pointing data and each descriptor, and   a data buffer,   wherein the data in the system memory is read to the data buffer in accordance with the fourth descriptor, and the data in the data buffer is transferred to the memory device in accordance with the third descriptor when the data is written into the memory device, and   the data in the memory device is read to the data buffer in accordance with the third descriptor, and the data in the data buffer is transferred to the system memory in accordance with the fourth descriptor when the data is read from the memory device.   
     
     
       2. The host controller according to  claim 1 , wherein the fourth descriptor is programmed so that a sum of sizes of a plurality of scattered data equals to the block length indicated in the third descriptor. 
     
     
       3. The host controller according to  claim 1 , wherein the data transfer between the host controller and the memory device is started by a memory read/write command which is issued by command controller when setting information of the third descriptor to the register set is completed, and
 the memory device acquires information necessary for the data transfer from the command.   
     
     
       4. A method for transferring data between a memory device and a system memory executed by a host controller, the system memory storing first, third, and fourth descriptors, the method comprising:
 (1) loading the first descriptor including a plurality of pointers with attributes;   (2) acquiring a pointer from the loaded first descriptor, wherein the pointer indicates a leading region of the third descriptor;   (3) loading the third descriptor based on the pointer to issue a command, wherein the third descriptor includes command issue information and attributes;   (4) issuing a command according to the loaded third descriptor;   (5) loading the fourth descriptor based on the pointer, wherein the fourth descriptor includes a number of DMA execution information and attributes;   (6) when the issued command is a read-command, reading data from the system memory to a data buffer in accordance with the fourth descriptor and transferring the data from the data buffer to the memory device in accordance with the third descriptor;   when the issued command is a write-command, reading data from the memory device to the data buffer in accordance with the third descriptor, and transferring the data from the data buffer to the system memory in accordance with the fourth descriptor;   (7) repeating (2) to (6) until an attribute of the first descriptor indicates the end of descriptor; and   (8) generating an interrupt when a data transfer is end or during a DMA data transfer,   wherein the third descriptor includes information to generate a data transfer command of the memory device, a command argument, a command number, a block length, and the number of blocks,   wherein the fourth descriptor includes information to designate system memory areas addresses, and sizes for each of a plurality of scattered data in the system memory.   
     
     
       5. The method according to  claim 4 , wherein the first, third, and fourth descriptors includes:
 information for indicating the type of descriptor; and   an end bit indicating the last descriptor for each of the first, third, and fourth descriptors.   
     
     
       6. A DMA transfer control method comprising:
 loading, from a memory, a second descriptor pointer described first among a plurality of second descriptor pointers described in a first descriptor, the first descriptor including a set of a plurality of pointers indicating a plurality of second descriptors;   loading, from the memory, a second descriptor indicated by the loaded second descriptor pointer;   loading, from the memory, a third descriptor described at a head of the second descriptor, writing contents of the third descriptor in a register, and issuing a command, the third descriptor including information for issuing an SD command;   loading a fourth descriptor from the memory, loading data indicated by an address described in the fourth descriptor, and transferring the data between a system memory and a buffer, the fourth descriptor including information indicating addresses and sizes of a plurality of data arranged in the system memory; and   repeating the above-mentioned operation, and generating an interrupt when all the data has been transferred.    
     
     
       7. The method according to claim 6, wherein
 the information for issuing the SD command is a command number, a command operation mode, and an argument, and   the third descriptor further includes information for transferring the data, the information for transferring the data being a block length and a number of blocks.    
     
     
       8. The method according to claim 7, wherein one SD command is issued by writing the third descriptor in the register set.  
     
     
       9. The method according to claim 8, wherein a host controller includes an SD command generation unit of the register set.  
     
     
       10. The method according to claim 6, one continuous region of an SD memory card can be designated by one of read/write commands.  
     
     
       11. The method according to claim 6, wherein a host driver activates the DMA transfer.  
     
     
       12. The method according to claim 6, wherein a controller including the DMA transfer generates the interrupt.  
     
     
       13. The method according to claim 12, wherein each of the first descriptor, the second descriptor, the third descriptor, and the fourth descriptor has attribute information containing information for identifying a type of descriptor, and information indicating an end position of the descriptor.