Semiconductor device

Abstract

A semiconductor device includes: various types of memories; an interface configured to transmit memory characteristic information of the memories to a host, receive information needed to control operations of the memories from the host, and perform interfacing between the host and the memories; and a controller configured to control operations of the memories in response to information received from the host, and control an operation of the interface.

What is claimed is: 
     
       1. A semiconductor device comprising:
 various types of memories; 
 an interface circuitry configured to transmit memory characteristic information of the memories to a host, receive information needed to control operations of the memories from the host, and perform interfacing between the host and the memories; and 
 a controller circuitry configured to control operations of the memories in response to information received from the host, and control an operation of the interface, 
 wherein the controller circuitry further includes: 
 a storage circuit configured to store the memory characteristic information generated for each a channel and an AC parameter generated for each memory the memories on the basis of the memory characteristic information to adjust data signals, 
 wherein the memories are implemented on a single card and include: 
 master memory circuitry configured to communicate with the host through the interface, and include various types of master memories; and 
 a slave memory circuitry coupled to the master memory circuitry through a relay, and configured to include various types of slave memories, 
 wherein the same type of memories from among the various types of master memories and the various types of slave memories are interconnected through the relay within one channel. 
 
     
     
       2. The semiconductor device according to  claim 1 , wherein the memories include:
 a master memory configured to communicate with the host through the interface, and include various types of master memory; and   a slave memory coupled to the master memory through a relay, configured to include various types of slave memories.   
     
     
       3. The semiconductor device according to  claim 2 , wherein the same type of memories from among the various types of master memories and the various types of slave memories are interconnected through the relay within one channel. 
     
     
       4. The semiconductor device according to  claim 1 , wherein the storage circuit is configured to store at least one of data, command, and address for the memories, wherein the data, the command, and the address are generated on the basis of the AC parameter. 
     
     
       5. The semiconductor device according to  claim 1 , wherein the controller circuitry is configured to transmit information stored in the storage circuit to the host through the interface circuitry according to a predetermined operation period. 
     
     
       6. The semiconductor device according to  claim 1 , wherein the controller circuitry is configured to select an operation mode of the interface circuitry according to characteristic information of at least one of capacity, speed, latency, and operation voltage of the memories. 
     
     
       7. The semiconductor device according to  claim 1 , wherein the controller circuitry is configured to transmit the memory characteristic information and operation information to the host through the interface circuitry, upon receiving a signal for requesting the memory characteristic information from the host. 
     
     
       8. The semiconductor device according to  claim 1 , wherein the controller circuitry is configured to control an operation of at least one of a data size, a transfer rate, address mapping, a refresh operation, data transmission, and protocol conversion of the memories. 
     
     
       9. The semiconductor device according to  claim 1 , wherein the memory characteristic information further includes information of at least one of position information, type information, and capacity information of the memories. 
     
     
       10. The semiconductor device according to  claim 1 , wherein the interface circuitry is configured to perform address remapping on the basis of type information of the memories. 
     
     
       11. The semiconductor device according to  claim 1 , wherein the interface circuitry is configured to check a connection state of the memories for each the channel. 
     
     
       12. The semiconductor device according to  claim 1 , wherein the interface circuitry includes:
 a unified circuit device controlled by the controller, configured to perform signal conversion in response to characteristic information of the memories. 
 
     
     
       13. The semiconductor device according to  claim 12 , wherein the unified circuit device includes a physical layer. 
     
     
       14. The semiconductor device according to  claim 12 , wherein the unified circuit device includes a plurality of operation modes, and selects any one of the plurality of operation modes according to a control signal of the controller circuitry. 
     
     
       15. The semiconductor device according to  claim 12 , wherein the unified circuit device operates in a first operation mode during a predetermined time, and enters and operates in a second operation mode after lapse of the first operation mode. 
     
     
       16. The semiconductor device according to  claim 15 , wherein the first operation mode and the second operation mode are operated in any one of a low clock frequency mode and a high clock frequency mode. 
     
     
       17. The semiconductor device according to  claim 15 , wherein the first operation mode and the second operation mode are operated in any one of a mode in which information stored in the controller circuitry is transmitted to the host and the other mode in which user data stored in the memories is transmitted to the host. 
     
     
       18. A semiconductor device comprising:
 a controller circuitry configured to store memory characteristic information regarding various types of memories, and output a control signal corresponding to the stored information; and 
 an interface circuitry configured to perform interfacing between a host and the various types of memories, and control operation modes of the various types of memories in response to the control signal, 
 wherein the controller circuitry further includes: 
 a storage circuit configured to store the memory characteristic information generated for each a channel and an AC parameter generated for each memory the memories on the basis of the memory characteristic information to adjust data signals, 
 wherein the memories are implemented on a single card and includes: 
 a master memory circuitry configured to communicate with the host through the interface, and include various types of master memories; and 
 a slave memory circuitry coupled to the master memory circuitry through a relay, and configured to include various types of slave memories, 
 wherein the same type of memories from among the various types of master memories and the various types of slave memories are interconnected through the relay within one channel. 
 
     
     
       19. The semiconductor device according to  claim 18 , wherein the storage circuit is configured to store at least one of data, command, and address for the memories, wherein the data, the command, and the address are generated on the basis of the AC parameter. 
     
     
       20. A semiconductor device comprising:
 various types of memories; 
 a controller circuitry configured to store memory characteristic information regarding the memories, and output a control signal corresponding to the stored information; and a unified circuit device configured to receive information needed to control operation modes of the memories, select any one operation mode corresponding to the memory characteristic information of the memories from among the plurality of operation modes in response to the control signal, and perform interfacing using the selected operation mode, 
 wherein the controller circuitry further includes: 
 a storage circuit configured to store the memory characteristic information generated for each a channel and an AC parameter generated for each memory the memories on the basis of the memory characteristic information to adjust data signals, 
 wherein the memories are implemented on a single card and include: 
 a master memory circuitry configured to communicate with the host through the interface, and include various types of master memories; and 
 a slave memory circuitry coupled to the master memory through a relay, and configured to include various types of slave memories, 
 wherein the same type of memories from among the various types of master memories and the various types of slave memories are interconnected through the relay within one channel.