Semiconductor memory device

Abstract

A CRC code is generated from an original data, a BCH code is generated with respect to the original data and the CRC code, and the original data, the CRC code, and the BCH code are recorded in pages selected from different planes of a plurality of memory chips. An RS code is generated from the original data across pages, a CRC code is generated with respect to the RS code, a BCH code is generated with respect to the RS code and the CRC code, and the RS code, the CRC code, the BCH code are recorded in a memory chip different from a memory chip including the original data. When reading data, error correction is performed on the original data by using the BCH code, and then CRC is calculated. If the number of errors is the number of errors that is correctable by erasure correction using the RS code, the original data is corrected by the erasure correction. If the number of errors exceeds an erasure correction capability of the RS code, normal error correction using the RS code is performed, and further error correction using the BCH code is performed.

What is claimed is: 
     
       1. A semiconductor memory device comprising:
 a plurality of memory chip chips, each chip having a plurality of pages; 
 a first encoder/decoder (E/D) encoder configured to obtain which obtains a first error check code and a first error correction code based on an original data, wherein the original data, the first error check code, and the first error correction code are recorded on a first page of a first memory chip; 
 ana second encoder configured to obtainwhich obtains a second error correction code for the original data, wherein the type of the second error correction is different from the type of the first error correction; and 
 a second E/D third encoder configured to obtain which obtains a second error check code and a third error correction code based on the second error correction code, wherein, the second error correction code, the second error check code, and the third error correction code are recorded on a second page of a second memory chip; 
 a first decoder which decodes the first error correction code recorded on the first page of the first memory chip and performs an error correction for the original data and the first error check code; 
 a second decoder which decodes the third error correction code recorded on the second page of the second memory chip and performs an error correction for the second error check code and the second error correction code; 
 a third decoder which decodes the first error check code and performs a first error check on a decoding result by the first decoder; 
 a fourth decoder which decodes the second error check code and performs a second error check on a decoding result by the second decoder; and 
 a fifth decoder which decodes the second error correction code across the pages of the plurality of the memory chips, based on a result that is a sum of error number obtained from the error check by the third decoder and the fourth decoder, 
 wherein a data block of the second error correction code is recorded in the second page of the second memory chip in which an error-expected value is smaller than an average value of error-expected values of pages in the second memory chip. 
 
     
     
       2. The device of  claim 1 , wherein
 the first E/D encoder obtains the first error check code based on the original data and obtains the first error correction code based on the original data and the first error check code, and the second E/D third encoder obtains the second error check code based on the second error correction code and obtains the third error correction code based on the second error correction code and the second error check code. 
 
     
     
       3. The device of  claim 2 , wherein
 a size of a data block of the original data and a size of a data block of the second error correction code are the same. 
 
     
     
       4. The device of  claim 3 , wherein
 the second error correction code is formed across a plurality of pages in a direction crossing data blocks of the original data. 
 
     
     
       5. The device of  claim 1 , wherein
 the data block of the second error correction code is recorded in a page having an error-expected value smaller than an average value of error-expected values of pages in a memory chip.   
     
     
       6. A memory device comprising:
 a plurality of first chips and a second chip, each chip including at least one memory having a plurality of planes, each plane comprising a plurality of data blocks, and each data block comprising an array of memory cells arranged in a plurality of pages;   an encoder coupled with the memories of the first chips and the second chip, the encoder:
 accessing first data associated with a page of the plurality of pages of the chips, 
 generating first error-correction codes based on the first data and generate first error check codes, 
 accessing second data associated with at least two pages of the plurality of pages of the chips, and 
 generating second error-correction codes based on the second data; 
   a controller coupled with the encoder and the memories of the first chips and the second chip to store at least a part of the first error-correction codes in a first page of the plurality of pages in the first chips and the second chip and to store at least a part of the second error-correction codes in a second page of the plurality of pages in the second chip; and   a decoder coupled with the controller and the memories of the first chips and the second chip, the decoder decoding the part of the first error correction codes from the first chips and the second chip in a page direction and decoding the second error correction codes from the first chips and the second chip across in a cross direction to the page direction, the decoding of the second error correction code being based on a result of a sum of error number obtained from an error check of the first chips and the second chip,   wherein the decoding the first error correction codes in the page direction and the decoding the second error correction codes in the cross direction to the page direction are repeatedly performed.    
     
     
       7. The memory device of claim 6, wherein the encoder is configured to:
 retrieve, from the second data, a first symbol associated with a first page of the plurality of pages;   retrieve, from the second data, a second symbol associated with a second page of the plurality of pages; and   generate the second error-correction codes based on the first symbol and the second symbol.    
     
     
       8. The memory device of claim 6, wherein the encoder is configured to:
 retrieve, from the second data, a first plurality of symbols associated with a first page of the plurality of pages;   retrieve, from the second data, a second plurality of symbols associated with a second page of the plurality of pages; and   generate the second error-correction codes based on the first plurality of symbols and the second plurality of symbols.    
     
     
       9. The memory device of claim 6, wherein the encoder is configured to:
 retrieve, from the second data, a first data portion associated with a first page of a first data block of the plurality of data blocks;   retrieve, from the second data, a second data portion associated with a first page of a second data block of the plurality of data blocks; and   generate the second error-correction codes based on the first data portion and the second data portion.    
     
     
       10. The memory device of claim 6, wherein the plurality of first chips and the second chip respectively correspond to a plurality of first memory chips and a second memory chip; wherein the encoder is configured to:
 retrieve, from the second data, a first data portion associated with a first page of the first memory chips;   retrieve, from the second data, a second data portion associated with a second page of the second memory chip; and   generate the second error-correction codes based on the first data portion and the second data portion.    
     
     
       11. The memory device of claim 6,
 wherein the plurality of pages comprises a plurality of upper bit pages and a plurality of lower bit pages;   wherein the plurality of upper bit pages comprises a first set of bits associated with each of the plurality of pages;   wherein the plurality of lower bit pages comprises a second set of bits associated with each of the plurality of pages; and   wherein the first set of bits are associated with a first word line, and the second set of bits are associated with a second word line.    
     
     
       12. The memory device of claim 11, wherein the plurality of upper bit pages comprises an upper bit page associated with a first data block and the plurality of lower bit pages comprises a lower bit page associated with a second data block
 wherein the encoder is configured to:
 retrieve, from the second data, a first data portion associated with the upper bit page; 
 retrieve, from the second data, a second data portion associated with the lower bit page; and 
 generate the second error-correction codes based on the first data portion and the second data portion.  
   
     
     
       13. The memory device of claim 11, wherein the plurality of first chips and the second chip respectively correspond to a first memory chip and a second memory chip; wherein the plurality of upper bit pages comprises an upper bit page associated with the first memory chip and the plurality of lower bit pages comprises a lower bit page associated with the second memory chip;
 wherein the encoder is configured to:
 retrieve, from the second data, a first data portion associated with the upper bit page; 
 retrieve, from the second data, a second data portion associated with the lower bit page; and 
 generate the second error-correction codes based on the first data portion and the second data portion.  
   
     
     
       14. The memory device of claim 6, wherein the encoder is configured to generate the first error-correction codes using at least one of: Cyclic Redundancy Check codes, Reed-Solomon codes, Bose-Chaudhuri-Hocquenghem codes, and Low-Density Parity-Check codes.  
     
     
       15. The memory device of claim 6, wherein the second data comprises at least a part of the first error-correction codes.  
     
     
       16. The memory device of claim 6, wherein the second data comprises at least a part of the first data.  
     
     
       17. The memory device of claim 6, wherein the encoder is configured to generate second error-correction codes based on at least a part of the second data associated with one page of the plurality of pages.  
     
     
       18. The memory device of claim 6, wherein the encoder is configured to generate error check codes based on at least one of the first and second data.  
     
     
       19. The memory device of claim 6, wherein the decoder is configured to:
 determine, based on the error check codes, whether the errors can be corrected using the first error-correction codes;   if the errors cannot be corrected using the first error-correction codes, correct the errors using the second error-correction codes and the error check codes.    
     
     
       20. The memory device of claim 6, wherein the encoder is configured to access the first and second data from a buffer memory.  
     
     
       21. A method performed at a memory device comprising one or more first chips and a second chip, each chip comprising at least one memory having memory cells having a plurality of planes, each plane comprising a plurality of data blocks, and each data block comprising an array of the memory cells arranged in a plurality of pages, the device further comprising an encoder which generates codes, a decoder which decodes the generated codes, and a controller which controls recording and reading of data to and from the memories and controls operation of the encoder and the decoder, the encoder and the decoder being coupled with the controller and the memories of the first chips and the second chip,
 the method comprising:   generating first error-correction codes based on first data associated with a page of the plurality of pages of the first chips and generating second error-correction codes based on second data associated with at least two pages of the plurality of pages of the first chips, the second error correction codes are different from the first error correction codes,   storing at least a part of the first error-correction codes in a first page of the plurality of pages in the first and second chips and at least a part of the second error-correction codes in a second page of the plurality of pages in the second chip, and   decoding a part of the first error correction codes from the first and the second chips in a page direction and decoding a part of the second error correction codes from the first chips and the second chip across in a cross direction to the page direction, the decoding of the second error correction code being based on a result of a sum of error number obtained from an error check of the first chips and the second chip,   wherein the decoding the part of the first error correction codes based on the first data in the page direction and the decoding the part of the second error correction codes based on the second data across in the cross direction to the page direction are repeatedly performed.    
     
     
       22. The method of claim 21, further comprising:
 retrieving, from the second data, a first symbol associated with a first page of the plurality of pages;   retrieving, from the second data, a second symbol associated with a second page of the plurality of pages; and   generating the second error-correction codes based on the first symbol and the second symbol.    
     
     
       23. The method of claim 21, further comprising:
 retrieving, from the second data, a first plurality of symbols associated with a first page of the plurality of pages;   retrieving, from the second data, a second plurality of symbols associated with a second page of the plurality of pages; and   generating the second error-correction codes based on the first plurality of symbols and the second plurality of symbols.    
     
     
       24. The method of claim 21, further comprising:
 retrieving, from the second data, a first data portion associated with a first page of a first data block of the plurality of data blocks;   retrieving, from the second data, a second data portion associated with a first page of a second data block of the plurality of data blocks; and   generating the second error-correction codes based on the first data portion and the second data portion.    
     
     
       25. The method of claim 21, wherein the one or more first chips and the second chip respectively corresponding to a first memory chip and a second memory chip, the method further comprising:
 retrieving, from the second data, a first data portion associated with a first page of the first memory chip of the at least one memory;   retrieving, from the second data, a second data portion associated with a second page of the second memory chip of the at least one memory; and   generating the second error-correction codes based on the first data portion and the second data portion.    
     
     
       26. The method of claim 21, further comprising:
 retrieving, from the second data, a first data portion associated with an upper bit page of a first data block of the at least one memory;   retrieving, from the second data, a second data portion associated with a lower bit page of a second data block of the at least one memory; and   generating the second error-correction codes based on the first data portion and the second data portion;   wherein the upper bit page comprises a first set of bits associated with each of the plurality of pages and the lower bit page comprises a second set of bits associated with each of the plurality of pages; wherein the first set of bits and the second set of bits are associated with, respectively, a first word line and a second word line.    
     
     
       27. The method of claim 21, wherein the one or more first chips and the second chip respectively correspond to a first memory chip and a second memory chip, the method further comprising:
 retrieving, from the second data, a first data portion associated with an upper bit page of the first memory chip of the at least one memory;   retrieving, from the second data, a second data portion associated with a lower bit page of the second memory chip of the at least one memory; and   generating the second error-correction codes based on the first data portion and the second data portion;   wherein the upper bit page comprises a first set of bits associated with each of the plurality of pages and the lower bit page comprises a second set of bits associated with each of the plurality of pages; wherein the first set of bits and the second set of bits are associated with, respectively, a first word line and a second word line.    
     
     
       28. The method of claim 21, wherein the first error-correction codes are generated using at least one of: Cyclic Redundancy Check codes, Reed-Solomon codes, Bose-Chaudhuri-Hocquenghem codes, and Low-Density Parity-Check codes.  
     
     
       29. The method of claim 21, wherein the second data comprises at least a part of the first error-correction codes.  
     
     
       30. The method of claim 21, wherein the second data comprises at least a part of the first data.  
     
     
       31. The method of claim 21, wherein the second error-correction codes are generated based on at least a part of the second data associated with one page of the plurality of pages.  
     
     
       32. The method of claim 21, further comprising: generating error check codes based on at least one of the first and second data.  
     
     
       33. The method of claim 32, further comprising:
 decoding the first error-correction codes and the second error-correction codes; and   correcting errors using the error check codes and at least one of the first error-correction codes the second error-correction codes.    
     
     
       34. The method of claim 33, further comprising:
 determining, based on the error check codes, whether the errors can be corrected using the first error-correction codes;   if the errors cannot be corrected using the first error-correction codes, correcting the errors using the second error-correction codes and the error check codes.    
     
     
       35. The method of claim 21, wherein the first and second data are accessed from a buffer memory.