Semiconductor memory card

Abstract

According to one embodiment, a semiconductor memory card includes a first pin group which includes a plurality of pins arranged in a line at an end portion on a side of an inserting direction into a connector and part of which is used both in a first and second modes; and a second pin group which includes a plurality of pins including at least two pin pairs for differential signal, is arranged so that a ground is positioned on both sides of each of the pin pairs for differential signal, and is used only in the second mode. In the second mode, among the respective pins configuring the first pin group, any of adjacent two pins are changed to a pin pair for differential clock signal, and a function of remaining pins of the first pin group is stopped.

What is claimed is: 
     
       1. A semiconductor memory card that includes a semiconductor memory that is mounted on one surface of a substrate and a controller that is mounted on the other surface of the substrate and controls the semiconductor memory, and is capable of operating in a first mode and a second mode in which data is transferred at a higher speed than the first mode, comprising:
 a first pin group which includes a plurality of pins arranged in a line at an end portion on a side of an inserting direction into a connector, which functions as four data pins, one command pin, one power source pin, one clock pin, and two ground pins in the first mode, and part of which is used both in the first and second modes; and   a second pin group which includes a plurality of pins including at least two pin pairs for differential signal, is arranged so that a ground is positioned on both sides of each of the pin pairs for differential signal, and is used only in the second mode, wherein   in the second mode, among the respective pins configuring the first pin group, any of adjacent two out of ones that function as the data pins, the command pin, and the clock pin in the first mode are changed to a pin pair for differential clock signal to function as the pin pair for differential clock signal, and a function of remaining pins of the first pin group is stopped.   
     
     
       2. The semiconductor memory card according to  claim 1 , wherein the second pin group is arranged in approximately same direction as the first pin group at a position that is near a center in the inserting direction and near an end on an opposite side of the inserting direction. 
     
     
       3. The semiconductor memory card according to  claim 2 , wherein the second pin group is arranged to be divided into a plurality of rows in the inserting direction. 
     
     
       4. The semiconductor memory card according to  claim 1 , wherein the first pin group and the second pin group are arranged to sandwich a region on the substrate in which the controller is mounted. 
     
     
       5. The semiconductor memory card according to  claim 1 , wherein each of the pins forming the second pin group is arranged without being offset in a direction perpendicular to the inserting direction with respect to the pins forming the first pin group. 
     
     
       6. The semiconductor memory card according to  claim 1 , wherein the second pin group is arranged in a direction different from the first pin group. 
     
     
       7. The semiconductor memory card according to  claim 1 , wherein the second pin group is arranged in approximately same direction as the first pin group adjacently to the first pin group. 
     
     
       8. The semiconductor memory card according to  claim 7 , further comprising an upper case and a lower case that accommodates the substrate, wherein
 the lower case includes a thin portion in a region facing a region in which the first and second pin groups are formed, and   the first and second pin groups are exposed outside the upper case and the lower case via an opening provided in the thin portion.   
     
     
       9. The semiconductor memory card according to  claim 8 , wherein there is provided one said thin portion commonly to all of the pins of the first and second pin groups. 
     
     
       10. The semiconductor memory card according to  claim 8 , wherein each of the pins forming the second pin group is arranged adjacently in the inserting direction with respect to the pins forming the first pin group, and the thin portion is formed commonly to a plurality of pins adjacent in the inserting direction. 
     
     
       11. The semiconductor memory card according to  claim 1 , wherein an area of each of the pins forming the second pin group is smaller than an area of each of the pins forming the first pin group. 
     
     
       12. The semiconductor memory card according to  claim 1 , wherein wires that connect respective pins for differential signal of the second pin group and the controller are formed on the substrate to have approximately equal length. 
     
     
       13. The semiconductor memory card according to  claim 1 , wherein wires that connect respective pins for differential signal of the second pin group and the controller are formed approximately in parallel on the substrate for each of the pin pairs. 
     
     
       14. The semiconductor memory card according to  claim 1 , wherein wires that connect respective pins for differential signal of the second pin group and the controller have approximately equal length and are formed approximately in parallel on the substrate for each of the pin pairs. 
     
     
       15. The semiconductor memory card according to  claim 1 , wherein each wire that connects each of the four data pins of the first pin group and the controller, a wire that connects the clock pin and the controller, and a wire that connects the command pin and the controller are formed on the substrate to have approximately equal length. 
     
     
       16. The semiconductor memory card according to  claim 1 , further comprising a case that accommodates the substrate, wherein
 an outer shape of a side surface of the case is different from a case of a semiconductor memory card exclusively for the first mode at least at one part.   
     
     
       17. The semiconductor memory card according to  claim 16 , wherein the case includes a notch for distinguishing from the case of the semiconductor memory card exclusively for the first mode. 
     
     
       18. The semiconductor memory card according to  claim 1 , wherein at least one of a pin in the first pin group has a larger area than a pin of same function of the semiconductor memory card exclusively for the first mode. 
     
     
       19. The semiconductor memory card according to  claim 1 , wherein the semiconductor memory is a NAND-type flash memory. 
     
     
       20. A semiconductor memory card comprising:
 a substrate having a front edge, a back edge, a central portion, a first surface and a second surface, the front edge being an edge arranged on a side of an inserting direction into a connector, the back edge being an edge arranged on an opposite side of the front edge, the central portion being a portion arranged at a midpoint of the front edge and the back edge;   a first semiconductor memory package mounted on the first surface of the substrate with a first connection terminal of the first semiconductor memory package touched on a first pad on the first surface of the substrate, the first semiconductor memory package being arranged between the front edge and the central portion on the first surface of the substrate;   a second semiconductor memory package mounted on the first surface of the substrate with a second connection terminal of the second semiconductor memory package touched on a second pad on the first surface of the substrate, the second semiconductor memory package being arranged between the central portion and the back edge on the first surface of the substrate;   a controller chip mounted between the front edge and the central portion on the second surface of the substrate, the controller chip controlling the first and second semiconductor memory packages and being capable of operating in a first mode and a second mode in which data is transferred at a higher speed than the first mode, the controller chip having a rectangular shape with a first side and a second side, the first side being a side arranged on the side of the inserting direction, the second side being a side different from the first side, the controller chip having first terminals on the first side and second terminals on the second side;   a first pin group which includes a plurality of first pins arranged near the first side with aligning along the first side on the second surface to be electrically connected via first wires to the first terminals along the second surface of the substrate, the plurality of first pins functioning as four data pins, one command pin, one power source pin, one clock pin, and two ground pins in the first mode, part of the plurality of first pins being used both in the first and second modes;   a second pin group which includes a plurality of second pins arranged near the second side with aligning along the second side on the second surface to be electrically connected via second wires to the second terminals along the second surface of the substrate, which functions as at least two pin pairs for differential data signal so that a ground signal is positioned on both sides of each of the pin pairs for differential data signal, the plurality of second pins being used in the second mode; and   an exterior case housing the substrate, the exterior case covering the first semiconductor memory package and the second semiconductor memory package on a side of the first surface of the substrate, the exterior case covering the controller chip and exposing the plurality of first pins and the plurality of second pins on a side of the second surface of the substrate,   wherein the second side is a side on an opposite side of the inserting direction,   the first pin group and the second pin group are arranged to sandwich a region on the second surface of the substrate in which the controller chip is mounted.   
     
     
       21. The semiconductor memory card according to claim 20, wherein
 in the second mode, among the first pins, any of adjacent two out of ones that function as the data pins, the command pin, and the clock pin in the first mode are changed to a pin pairs for differential clock signal so that the pin pairs function as the pin pairs for differential clock signal, and a function of remaining pins of the first pin group is invalidated.   
     
     
       22. The semiconductor memory card according to claim 20, wherein
 the second pin group is arranged at a position that is offset from the central portion in the inserting direction and that is near the central portion of the substrate.   
     
     
       23. The semiconductor memory card according to claim 22, wherein
 the second pin group is arranged to be divided into a plurality of rows.   
     
     
       24. The semiconductor memory card according to claim 20, wherein
 each of the second pins is arranged without being offset in a direction perpendicular to the inserting direction with respect to the first pins.   
     
     
       25. The semiconductor memory card according to claim 20, wherein
 an area of each of the second pins is smaller than an area of each of the first pins.   
     
     
       26. The semiconductor memory card according to claim 20, wherein
 the second wires that connect respective second pins for differential data signal and the controller chip are formed on the second surface of substrate to have approximately equal length.   
     
     
       27. The semiconductor memory card according to claim 20, wherein
 the second wires that connect respective second pins for differential data signal and the controller chip are formed approximately in parallel on the substrate for each of the pin pairs.   
     
     
       28. The semiconductor memory card according to claim 20, wherein
 the second wires that connect respective second pins for differential data signal and the controller chip have approximately equal length and are formed approximately in parallel on the substrate for each of the pin pairs.   
     
     
       29. The semiconductor memory card according to claim 20, wherein
 each first wire that connects each of the four first pins for data and the controller chip, a first wire that connects the first pin for clock and the controller chip, and a first wire that connects the first pin for command and the controller chip are formed on the second surface of the substrate to have approximately equal length.   
     
     
       30. The semiconductor memory card according to claim 20, wherein,
 when seen through from a direction perpendicular to the first surface of the substrate, a side edge of the exterior case has an outer shape that indicates the exterior case is compatible with the second mode.   
     
     
       31. The semiconductor memory card according to claim 30, wherein
 the exterior case has a notch as the outer shape.   
     
     
       32. The semiconductor memory card according to claim 20, wherein
 at least one of first pins has an expanded portion that indicates the exterior case is compatible with the second mode.   
     
     
       33. The semiconductor memory card according to claim 20, wherein
 each of the first semiconductor memory package and the second semiconductor memory package includes a NAND-type flash memory.   
     
     
       34. The semiconductor memory card according to claim 20, wherein
 date transfer speed of the first mode is 20 Mbyte/sec, and   date transfer speed of the second mode is 300 Mbyte/sec.   
     
     
       35. A semiconductor memory card comprising:
 a substrate having a front edge, a back edge, a central portion, a first surface and a second surface, the front edge being an edge arranged on a side of an inserting direction into a connector, the back edge being an edge arranged on an opposite side of the front edge, the central portion being a portion arranged at a midpoint of the front edge and the back edge;   a first semiconductor memory package mounted on the first surface of the substrate with a first connection terminal of the first semiconductor memory package touched on a first pad on the first surface of the substrate, the first semiconductor memory package being arranged between the front edge and the central portion on the first surface of the substrate;   a second semiconductor memory package mounted on the first surface of the substrate with a second connection terminal of the second semiconductor memory package touched on a second pad on the first surface of the substrate, the second semiconductor memory package being arranged between the central portion and the back edge on the first surface of the substrate;   a controller mounted on the second surface of the substrate, the controller controlling the first and second semiconductor memory packages and being capable of operating in a first mode and a second mode in which data is transferred at a higher speed than the first mode, the controller having a rectangular shape with a first side and a second side, the first side being a side arranged on the side of the inserting direction, the second side being a side different from the first side, the controller having first terminals on the first side and second terminals on the second side;   a first pin group which includes a plurality of first pins arranged near the first side with aligning along the first side on the second surface to be electrically connected via first wires to the first terminals along the second surface of the substrate, the plurality of first pins functioning as four data pins, one command pin, one power source pin, one clock pin, and two ground pins in the first mode, part of the plurality of first pins being used both in the first and second modes; and   a second pin group which includes a plurality of second pins arranged near the second side with aligning along the second side on the second surface to be electrically connected via second wires to the second terminals along the second surface of the substrate, which functions as at least two pin pairs for differential data signal so that a ground signal is positioned on both sides of each of the pin pairs for differential data signal, the plurality of second pins being used in the second mode,   wherein in the second mode, among the respective first pins, any of adjacent two out of ones that function as the data pins, the command pin, and the clock pin in the first mode are changed to a pin pair for differential clock signal to function as the pin pair for differential clock signal, and a function of remaining pins of the first pin group is stopped,   the second side is a side on an opposite side of the inserting direction,   the first pin group and the second pin group are arranged to sandwich a region on the second surface of the substrate in which the controller is mounted.   
     
     
       36. A semiconductor memory card that includes a semiconductor memory mounted on a first surface of a substrate and a controller mounted on a second surface of the substrate, the controller controlling the semiconductor memory and being capable of operating in a first mode and a second mode in which data is transferred at a higher speed than the first mode, the substrate having a front edge, a back edge, a central portion, the first surface and the second surface, the front edge being an edge arranged on a side of an inserting direction into a connector, the back edge being an edge arranged on an opposite side of the front edge, the central portion being a portion arranged at a midpoint of the front edge and the back edge, the controller having a rectangular shape with a first side and a second side, the first side being a side arranged on the side of the inserting direction, the second side being a side different from the first side, the controller having first terminals on the first side and second terminals on the second side, the semiconductor memory card comprising:
 a first pin group which includes a plurality of first pins arranged near the first side with aligning along the first side on the second surface to be electrically connected via first wires to the first terminals along the second surface of the substrate, the plurality of first pins functioning as four data pins, one command pin, one power source pin, one clock pin, and two ground pins in the first mode, part of the plurality of first pins being used both in the first mode and the second mode; and   a second pin group which includes a plurality of second pins arranged near the second side with aligning along the second side on the second surface to be electrically connected via second wires to the second terminals along the second surface of the substrate, which functions as a pin pair for differential data signal and a pin pair for ground signal so that the pin pair for differential data signal is positioned between the pin pair for ground signal, a paired wires connected to the pin pair for differential signal is provided between a first wire connected the first ground pin and a second wire connected the second ground pin, the plurality of second pins being used in the second mode,   wherein in the second mode, among the respective first pins, any of adjacent two out of ones that function as the data pins, the command pin, and the clock pin in the first mode function as the pin pair for differential clock signal, and remaining first pins are invalidated,   the second side is a side on an opposite side of the inserting direction,   the first pin group and the second pin group are arranged to sandwich a region on the second surface of the substrate in which the controller is mounted.   
     
     
       37. The semiconductor memory card according to claim 36, wherein
 date transfer speed of the first mode is 20 Mbyte/sec, and   date transfer speed of the second mode is 300 Mbyte/sec.   
     
     
       38. A semiconductor memory card comprising:
 a substrate having a front edge, a back edge, a central portion, a first surface and a second surface, the front edge being an edge arranged on a side of an inserting direction into a connector, the back edge being an edge arranged on an opposite side of the front edge, the central portion being a portion arranged at a midpoint of the front edge and the back edge;   a first semiconductor memory package mounted on the first surface of the substrate with a first connection terminal of the first semiconductor memory package touched on a first pad on the first surface of the substrate, the first semiconductor memory package being arranged between the front edge and the central portion on the first surface of the substrate;   a second semiconductor memory package mounted on the first surface of the substrate with a second connection terminal of the second semiconductor memory package touched on a second pad on the first surface of the substrate, the second semiconductor memory package being arranged between the central portion and the back edge on the first surface of the substrate;   a controller chip mounted between the front edge and the central portion on the second surface of the substrate, the controller chip controlling the first and second semiconductor memory packages and being capable of operating in a first mode and a second mode in which data is transferred at a higher speed than the first mode, the controller chip having a rectangular shape with a first side and a second side, the first side being a side arranged on the side of the inserting direction, the second side being a side different from the first side, the controller chip having first terminals on the first side and second terminals on the second side;   a first pin group which includes a plurality of first pins arranged near the first side with aligning along the first side on the second surface to be electrically connected via first wires to the first terminals along the second surface of the substrate, the plurality of first pins functioning as four data pins, one command pin, one power source pin, one clock pin, and two ground pins in the first mode, part of the plurality of first pins being used both in the first and second modes;   a second pin group which includes a plurality of second pins arranged near the second side with aligning along the second side on the second surface to be electrically connected via second wires to the second terminals along the second surface of the substrate, which functions as at least two pin pairs for differential data signal so that a ground signal is positioned on both sides of each of the pin pairs for differential data signal, the plurality of second pins being used in the second mode; and   an exterior case housing the substrate, the exterior case covering the first semiconductor memory package and the second semiconductor memory package on a side of the first surface of the substrate, the exterior case covering the controller chip and exposing the plurality of first pins and the plurality of second pins on a side of the second surface of the substrate,   the substrate further has a side edge adjoining the front edge,   the second side is a side adjoining the first side,   the second pin group is arranged between the second side and the side edge.   
     
     
       39. The semiconductor memory card according to claim 38, wherein
 in the second mode, among the first pins, any of adjacent two out of ones that function as the data pins, the command pin, and the clock pin in the first mode are changed to a pin pairs for differential clock signal so that the pin pairs function as the pin pairs for differential clock signal, and a function of remaining pins of the first pin group is invalidated.   
     
     
       40. The semiconductor memory card according to claim 38, wherein
 the second pin group is arranged at a position that is offset from the central portion in the inserting direction and that is near the central portion of the substrate.   
     
     
       41. The semiconductor memory card according to claim 40, wherein
 the second pin group is arranged to be divided into a plurality of rows.   
     
     
       42. The semiconductor memory card according to claim 38, wherein
 each of the second pins is arranged without being offset in a direction perpendicular to the inserting direction with respect to the first pins.   
     
     
       43. The semiconductor memory card according to claim 38, wherein
 an area of each of the second pins is smaller than an area of each of the first pins.   
     
     
       44. The semiconductor memory card according to claim 38, wherein
 the second wires that connect respective second pins for differential data signal and the controller chip are formed on the second surface of substrate to have approximately equal length.   
     
     
       45. The semiconductor memory card according to claim 38, wherein
 the second wires that connect respective second pins for differential data signal and the controller chip are formed approximately in parallel on the substrate for each of the pin pairs.   
     
     
       46. The semiconductor memory card according to claim 38, wherein
 the second wires that connect respective second pins for differential data signal and the controller chip have approximately equal length and are formed approximately in parallel on the substrate for each of the pin pairs.   
     
     
       47. The semiconductor memory card according to claim 38, wherein
 each first wire that connects each of the four first pins for data and the controller chip, a first wire that connects the first pin for clock and the controller chip, and a first wire that connects the first pin for command and the controller chip are formed on the second surface of the substrate to have approximately equal length.   
     
     
       48. The semiconductor memory card according to claim 38, wherein,
 when seen through from a direction perpendicular to the first surface of the substrate, a side edge of the exterior case has an outer shape that indicates the exterior case is compatible with the second mode.   
     
     
       49. The semiconductor memory card according to claim 48, wherein
 the exterior case has a notch as the outer shape.   
     
     
       50. The semiconductor memory card according to claim 38, wherein
 at least one of first pins has an expanded portion that indicates the exterior case is compatible with the second mode.   
     
     
       51. The semiconductor memory card according to claim 38, wherein
 each of the first semiconductor memory package and the second semiconductor memory package includes a NAND-type flash memory.   
     
     
       52. The semiconductor memory card according to claim 38, wherein
 date transfer speed of the first mode is 20 Mbyte/sec, and   date transfer speed of the second mode is 300 Mbyte/sec.   
     
     
       53. A semiconductor memory card comprising:
 a substrate having a front edge, a back edge, a central portion, a first surface and a second surface, the front edge being an edge arranged on a side of an inserting direction into a connector, the back edge being an edge arranged on an opposite side of the front edge, the central portion being a portion arranged at a midpoint of the front edge and the back edge;   a first semiconductor memory package mounted on the first surface of the substrate with a first connection terminal of the first semiconductor memory package touched on a first pad on the first surface of the substrate, the first semiconductor memory package being arranged between the front edge and the central portion on the first surface of the substrate;   a second semiconductor memory package mounted on the first surface of the substrate with a second connection terminal of the second semiconductor memory package touched on a second pad on the first surface of the substrate, the second semiconductor memory package being arranged between the central portion and the back edge on the first surface of the substrate;   a controller mounted on the second surface of the substrate, the controller controlling the first and second semiconductor memory packages and being capable of operating in a first mode and a second mode in which data is transferred at a higher speed than the first mode, the controller having a rectangular shape with a first side and a second side, the first side being a side arranged on the side of the inserting direction, the second side being a side different from the first side, the controller having first terminals on the first side and second terminals on the second side;   a first pin group which includes a plurality of first pins arranged near the first side with aligning along the first side on the second surface to be electrically connected via first wires to the first terminals along the second surface of the substrate, the plurality of first pins functioning as four data pins, one command pin, one power source pin, one clock pin, and two ground pins in the first mode, part of the plurality of first pins being used both in the first and second modes; and   a second pin group which includes a plurality of second pins arranged near the second side with aligning along the second side on the second surface to be electrically connected via second wires to the second terminals along the second surface of the substrate, which functions as at least two pin pairs for differential data signal so that a ground signal is positioned on both sides of each of the pin pairs for differential data signal, the plurality of second pins being used in the second mode,   wherein in the second mode, among the respective first pins, any of adjacent two out of ones that function as the data pins, the command pin, and the clock pin in the first mode are changed to a pin pair for differential clock signal to function as the pin pair for differential clock signal, and a function of remaining pins of the first pin group is stopped,   the substrate further has a side edge adjoining the front edge,   the second side is a side adjoining the first side,   the second pin group is arranged between the second side and the side edge.   
     
     
       54. A semiconductor memory card that includes a semiconductor memory mounted on a first surface of a substrate and a controller mounted on a second surface of the substrate, the controller controlling the semiconductor memory and being capable of operating in a first mode and a second mode in which data is transferred at a higher speed than the first mode, the substrate having a front edge, a back edge, a central portion, the first surface and the second surface, the front edge being an edge arranged on a side of an inserting direction into a connector, the back edge being an edge arranged on an opposite side of the front edge, the central portion being a portion arranged at a midpoint of the front edge and the back edge, the controller having a rectangular shape with a first side and a second side, the first side being a side arranged on the side of the inserting direction, the second side being a side different from the first side, the controller having first terminals on the first side and second terminals on the second side, the semiconductor memory card comprising:
 a first pin group which includes a plurality of first pins arranged near the first side with aligning along the first side on the second surface to be electrically connected via first wires to the first terminals along the second surface of the substrate, the plurality of first pins functioning as four data pins, one command pin, one power source pin, one clock pin, and two ground pins in the first mode, part of the plurality of first pins being used both in the first mode and the second mode; and   a second pin group which includes a plurality of second pins arranged near the second side with aligning along the second side on the second surface to be electrically connected via second wires to the second terminals along the second surface of the substrate, which functions as a pin pair for differential data signal and a pin pair for ground signal so that the pin pair for differential data signal is positioned between the pin pair for ground signal, a paired wires connected to the pin pair for differential signal is provided between a first wire connected the first ground pin and a second wire connected the second ground pin, the plurality of second pins being used in the second mode,   wherein in the second mode, among the respective first pins, any of adjacent two out of ones that function as the data pins, the command pin, and the clock pin in the first mode function as the pin pair for differential clock signal, and remaining first pins are invalidated,   the substrate further has a side edge adjoining the front edge,   the second side is a side adjoining the first side,   the second pin group is arranged between the second side and the side edge.   
     
     
       55. The semiconductor memory card according to claim 54, wherein
 date transfer speed of the first mode is 20 Mbyte/sec, and   date transfer speed of the second mode is 300 Mbyte/sec.