Use of a recirculating delay line with a time-to-digital converter

Abstract

The resolution of a time to digital converter (TDC) is improved by using a gain stage at the input of the fine TDC. A delay line receives a pulse corresponding to the time information and recirculates the pulse in the delay line by coupling an output of the delay line to an input of the delay line. An integrating fine TDC receives a number of pulses from the delay line corresponding to the desired gain.

What is claimed is: 
     
       1. A method for performing a time to digital conversion comprising:
 receiving an input pulse indicative of time information; 
 recirculating a representation of the input pulse in at least one delay line; 
 generating an output pulse corresponding to the input pulse based, at least in part, on a delay line output signal of the at least one delay line; and 
 supplying the output pulse N times to an integrator, where N is an integer greater than one. 
 
     
     
       2. The method as recited in  claim 1  wherein recirculating the representation of the input pulse in the at least one delay line further comprises:
 logically combining a first input signal to the at least one delay line with a second input signal based on the delay line output signal. 
 
     
     
       3. The method as recited in  claim 1  further comprising:
 selectively supplying the output pulse to the integrator N times according to an enable signal. 
 
     
     
       4. The method as recited in  claim 1  further comprising:
 determining a polarity of the input pulse. 
 
     
     
       5. The method as recited in  claim 1  further comprising:
 detecting a rising edge of the input pulse and generating a rising edge pulse; 
 detecting a falling edge of the input pulse and generating a falling edge pulse; 
 logically combining a feedback signal based on the delay line output signal and at least the rising edge pulse to generate a delay line input signal; and 
 supplying the delay line input signal to an input of the at least one delay line. 
 
     
     
       6. The method as recited in  claim 5  further comprising selecting one of a first delay path and a second delay path in a feedback path coupled between the delay line output signal and the input of the at least one delay line. 
     
     
       7. The method as recited in  claim 5  further comprising logically combining the feedback signal based on the delay line output signal, the rising edge pulse, and the falling edge pulse to generate the delay line input signal. 
     
     
       8. The method as recited in  claim 7  further comprising dividing the delay line output signal by two to generate the output pulse. 
     
     
       9. An apparatus comprising:
 a delay line; 
 input logic coupled to receive an input pulse and coupled to receive an output of the delay line, the input logic to supply a delay line input signal to the delay line, wherein a representation of the input pulse is recirculated in the delay line; and 
 an integrating time to digital converter coupled to the delay line to receive N pulse out signals, each pulse out signal corresponding to the input pulse to thereby generate a digital representation of the input pulse multiplied by a gain of N, where N is an integer greater than one. 
 
     
     
       10. The apparatus as recited in  claim 9  wherein the input logic comprises an OR gate to logically combine the delay line input signal with a feedback signal corresponding to the output of the delay line to recirculate the input pulse. 
     
     
       11. The apparatus as recited in  claim 10  further comprising:
 a first delay path and a second delay path in a feedback path between the output of the delay line and the input logic; and 
 a selector circuit to select the first or the second delay path. 
 
     
     
       12. The apparatus as recited in  claim 10  further comprising:
 a monostable multivibrator circuit coupled to the output of the delay line to generate the feedback signal. 
 
     
     
       13. The apparatus as recited in  claim 9  further comprising:
 output logic coupled to an output of the delay line to supply a pulse out signal according to an enable signal. 
 
     
     
       14. The apparatus as recited in  claim 9  further comprising:
 sign logic to determine a polarity of the input pulse and supply a sign indication. 
 
     
     
       15. The apparatus as recited in  claim 9  further comprising:
 a rising edge detector to detect a rising edge of the input pulse and supply a rising edge pulse; 
 a falling edge detector to detect a falling edge of the input pulse and generate a falling edge pulse; and 
 a logic circuit to logically combine a feedback signal based on the output of the delay line, the rising edge pulse, and the falling edge pulse to generate the delay line input signal. 
 
     
     
       16. The apparatus as recited in  claim 15  further comprising a divide by two circuit to divide the output of the delay line by two to generate a pulse out signal. 
     
     
       17. The apparatus as recited in  claim 16  further comprising a gating circuit to selectively pass the pulse out signal N times according to an enable signal, to thereby effectively supply the input pulse N times to the integrating time to digital converter. 
     
     
       18. The apparatus as recited in  claim 9  further comprising:
 a second delay line; 
 a rising edge detector to detect a rising edge of the input pulse and supply a rising edge pulse; 
 a falling edge detector to detect a falling edge of the input pulse and generate a falling edge pulse; 
 a first logic circuit to logically combine an output of the delay line and the rising edge pulse to generate the delay line input signal; 
 a second logic circuit to logically combine an output of the second delay line and the falling edge pulse to generate a second delay line input signal; and 
 a logic circuit to combine the output of the delay line and the output of the second delay line into an output pulse supplied to the integrating time to digital converter as the representation of the input pulse for each of the pulse out signals. 
 
     
     
       19. An apparatus comprising:
 a delay line supplying a delay line output signal; 
 a rising edge detector to detect a rising edge of an input pulse and supply a rising edge pulse; 
 a falling edge detector to detect a falling edge of the input pulse and generate a falling edge pulse; 
 a first logic circuit to logically combine the rising edge pulse, the falling edge pulse, and a feedback signal based on the delay line output signal; and 
 a second logic circuit coupled to receive an enable signal and an output pulse based on the delay line output signal and to pass the output pulse when the enable signal is asserted. 
 
     
     
       20. The apparatus as recited in  claim 19  comprising:
 a divide by two circuit coupled to receive the delay line output signal and supply the output pulse to the second logic circuit.