Isolation region fabrication for replacement gate processing

Abstract

A semiconductor structure includes a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a bottom silicon layer, a buried oxide (BOX) layer, and a top silicon layer; a plurality of active devices formed on the top silicon layer; and an isolation region located between two of the active devices, wherein at least two of the plurality of active devices are electrically isolated from each other by the isolation region, and wherein the isolation region extends through the top silicon layer to the BOX layer.

The invention claimed is: 
     
       1. A semiconductor structure, comprising:
 a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a bottom silicon layer, a buried oxide (BOX) layer, and a top silicon layer;   a plurality of active devices formed on the top silicon layer; and   an isolation region located between two of the plurality of active devices, wherein at least two of the plurality of active devices are electrically isolated from each other by the isolation region, wherein the isolation region extends through the top silicon layer to the BOX layer, wherein the isolation region further extends between a pair of spacers that are located on the top silicon layer on either side of the isolation region, and wherein the isolation region further extends through an interlevel dielectric (ILD) layer that is located over the pair of spacers.   
     
     
       2. The semiconductor structure of  claim 1 , further comprising a hardmask layer located over the isolation region. 
     
     
       3. The semiconductor structure of  claim 2 , wherein the hardmask layer comprises silicon nitride. 
     
     
       4. A semiconductor device comprising:
 a substrate including a top silicon layer that includes a fin;   a first gate structure disposed on the fin;   a second gate structure disposed on the fin;   an isolation region disposed between the first gate structure and the second gate structure;   a first spacer disposed on a first side of the isolation region and disposed on the top silicon layer;   a second spacer disposed on a second side of the isolation region and disposed on the top silicon layer; and   an interlevel dielectric (ILD) layer disposed on the first spacer and the second spacer,   wherein the isolation region extends between the first spacer and the second spacer, and   wherein the isolation region extends through the ILD layer that is disposed on the first spacer and the second spacer.    
     
     
       5. The semiconductor device of claim 4, wherein the isolation region includes silicon nitride.  
     
     
       6. The semiconductor device of claim 4, wherein the isolation region is disposed below a silicon nitride layer.  
     
     
       7. The semiconductor device of claim 4, wherein the isolation region electrically isolates the first gate structure from the second gate structure.  
     
     
       8. The semiconductor device of claim 4, further comprising source/drain regions disposed on the substrate, disposed on sides of the first and second gate structures, and disposed below the first and second spacers.  
     
     
       9. The semiconductor device of claim 4, wherein the substrate is a silicon-on-insulator substrate.  
     
     
       10. The semiconductor device of claim 4, wherein a top surface of the isolation region is planarized.  
     
     
       11. The semiconductor device of claim 4, further comprising channels disposed below the first gate structure and the second gate structure.  
     
     
       12. The semiconductor device of claim 4, wherein the isolation region extends through the ILD layer in a direction that is substantially parallel with respect to a top surface of the substrate.  
     
     
       13. The semiconductor device of claim 4, wherein the isolation region extends through the ILD layer in a direction that is substantially perpendicular with respect to a top surface of the substrate.  
     
     
       14. The semiconductor device of claim 4, wherein the ILD layer is disposed on a sidewall of the first spacer and on a sidewall of the second spacer.  
     
     
       15. The semiconductor device of claim 4, wherein the ILD layer is disposed on a top surface of the first spacer and on a top surface of the second spacer.  
     
     
       16. The semiconductor device of claim 4, wherein the isolation region contacts the ILD layer.