Flip chip and method of making flip chip

Abstract

Disclosed is a method for manufacturing a flip chip, in which a gold typically used in a flip chip manufacturing is adhered by conductive adhesives, wherein the method comprises steps of depositing a metal seed layer on a substrate; applying and patterning a photoresist or a dry film; forming a gold bump by electroplating; patterning the seed layer; forming an insulating layer on the seed layer and upper end of the gold bump; and patterning an insulating layer. Accordingly, it is possible to manufacture a flip chip, in which electrical function between bumps can be evaluated, with less cost.

The invention claimed is: 
     
       1. A flip chip comprising:
 an insulating layer arranged on and directly contacted with a substrate, wherein the insulating layer covers the substrate; 
 a metal patterned seed layer arranged on the insulating layer and directly contacted with the insulating layer; and 
 a plate bump layer formed on the metal patterned seed layer, wherein one two or more plate bumps are formed; 
 wherein a metal pattern is formed at a side of the two or more plate bump, bumps, and is formed by patterning a precursor of the metal patterned seed layer; wherein the metal pattern is at least a part of the metal patterned seed layer, and forms electrical connection between the plate bumps. 
 
     
     
       2. The flip chip as claimed in  claim 1 , wherein the substrate is one selected from the group consisting of a silicon wafer, a compound semiconductor, quartz, glass, and ceramic material. 
     
     
       3. The flip chip as claimed in  claim 1 , wherein the insulating layer comprises SiO 2  or Si 3 N 4 . 
     
     
       4. The flip chip as claimed in  claim 1 , wherein the seed layer comprises an adhesive layer and an electrode layer. 
     
     
       5. The flip chip as claimed in  claim 4 , wherein the adhesive layer comprises titanium, and the electrode layer comprises copper or gold. 
     
     
       6. A flip chip manufacturing method comprising:
 (a) forming a seed layer on a substrate by using a conductive thin layer;   (b) applying and patterning a photoresist or a dry film;   (c) forming gold bumps by electroplating;   (d) patterning the seed layer to form a metal pattern;   (e) forming an insulating layer on the seed layer and the upper end of the gold bumps; and   (f) applying and patterning a photoresist or a dry film so as to pattern the insulating layer;   wherein the metal pattern forms electrical connection between the gold bumps, and the polarity of the photoresist or a dry film in step b) is opposite to the polarity of photoresist or a dry film in step f).   
     
     
       7. The flip chip manufacturing method as claimed in  claim 6 , wherein the patterning of steps (b) and (f) are performed by photolithography. 
     
     
       8. The flip chip manufacturing method as claimed in  claim 7 , wherein a photolithography mask used in the patterning processes of step (b) is the same as that of step (f). 
     
     
       9. The flip chip manufacturing method as claimed in  claim 6 , wherein the patterning process of step (d) comprises applying and patterning a photoresist or a dry film and etching a portion of the conductive thin film on which portion the photoresist or the dry film is not, so as to form a metal pattern for electrical connection between gold bumps. 
     
     
       10. A flip chip comprising:
 a first insulating layer arranged on and directly contacted with a substrate, wherein the first insulating layer covers the substrate,   a metal patterned seed layer arranged on the first insulating layer and comprising a conductive metal directly contacted with the first insulating layer,   a plate bump layer formed on the metal patterned seed layer, wherein two or more plate bumps are formed with a horizontal gap therebetween and constitute the plate bump layer over the first insulating layer, wherein a metal pattern is formed at a side of the two or more plate bumps and is formed by patterning a precursor of the metal patterned seed layer, wherein the metal pattern is at least a part of the metal patterned seed layer and forms electrical connection between the two or more plate bumps, and   a second insulating layer formed over and covering the metal pattern such that the electrical connection electrically connecting between the two or more plate bumps is interposed between the first insulating layer and the second insulating layer, wherein the second insulating layer does not cover top surfaces of the two or more plate bumps.    
     
     
       11. The flip chip of claim 10, wherein the flip chip further comprises a third insulating layer that covers a portion of the first insulating layer on which the conductive metal of the metal pattern is not provided such that the third insulating layer directly contacts the first insulating layer without a conductive layer interposed therebetween.  
     
     
       12. The flip chip of claim 10, wherein the two or more plate bumps are made of at least one material selected from the group consisting of gold, copper and solder.  
     
     
       13. The flip chip of claim 10, wherein each of the first and second insulating layers comprises at least one selected from the group consisting of SiO 2  and Si 3 N 4 .  
     
     
       14. The flip chip of claim 10, wherein the metal patterned seed layer comprises an adhesive sublayer and an electrode sublayer that is thicker than the adhesive sublayer.  
     
     
       15. The flip chip of claim 14, wherein the adhesive layer comprises titanium, and the electrode layer comprises copper or gold.  
     
     
       16. A method of making the flip chip of claim 10, the method comprising:
 forming the first insulating layer over the substrate;   forming a conductive metal on the first insulating layer to provide a metal seed layer that is the precursor of the metal patterned seed layer;   forming a photoresist layer over the metal seed layer;   selectively patterning the photoresist layer to provide two or more openings that expose the metal seed layer through the photoresist layer;   electroplating to grow two or more plate bumps from the metal seed layer exposed through the two or more openings, in which the metal seed layer works as an electroplating electrode for the two or more plate bumps so that an electrode wire does not have to be formed for each of the two or more plate bumps;   subsequent to electroplating, removing the photoresist layer to provide an intermediate structure comprising the substrate, the first insulating layer over the substrate, the metal seed layer over the first insulating layer and the two or more plate bumps that are on the metal seed layer with a horizontal gap therebetween;   subsequent to removing the photoresist layer, patterning the metal seed layer to form an intermediate device with the metal pattern comprising the electrical connection connecting between the two or more plate bumps, wherein patterning the metal seed layer removes a portion of the conductive metal to expose the portion of the first insulating layer;   forming an insulating material over the intermediate device to provide the second insulating layer over the metal pattern and a third insulating layer over the portion of the first insulating layer, wherein forming the insulating material further forms a fourth insulating layer over the two or more plate bumps; and   removing the fourth insulating layer to expose a top portion of each of the two or more plate bumps.    
     
     
       17. The flip chip of claim 1, wherein the insulating layer is referred to as a first insulating layer,
 wherein the two or more plate bumps constitute the plate bump layer over the first insulating layer,   wherein the metal pattern is formed at a side of the two or more plate bumps when viewing in a direction from top of the plate bumps toward the substrate,   wherein the metal pattern is at least a part of the metal patterned seed layer and forms electrical connection between the two or more plate bumps,   wherein the flip chip further comprises a second insulating layer formed over and covering the metal pattern such that the metal pattern comprising the electrical connection between the two or more plate bumps is interposed between the first insulating layer and the second insulating layer.    
     
     
       18. The flip chip of claim 17, wherein the flip chip further comprises a third insulating layer formed over a portion of the first insulating layer on which the metal pattern is not provided such that no conductive layer is interposed between the first insulating layer and the third insulating layer, wherein the second insulating layer and the third insulating layer are formed together but at different levels from the substrate.  
     
     
       19. The flip chip of claim 17, wherein the two or more plate bumps are made of at least one material selected from the group consisting of gold, copper and solder.  
     
     
       20. The flip chip of claim 17, wherein each of the first and second insulating layer comprises at least one selected from the group consisting of SiO 2  and Si 3 N 4 .  
     
     
       21. The flip chip of claim 17, wherein the metal patterned seed layer comprises an adhesive layer and an electrode layer.  
     
     
       22. The flip chip of claim 21, wherein the adhesive layer comprises titanium, and the electrode layer comprises copper or gold.  
     
     
       23. A method of making the flip chip of claim 17, the method comprising:
 forming the first insulating layer over the substrate;   forming a conductive metal on the first insulating layer to provide a metal seed layer that is the precursor of the metal patterned seed layer;   forming a photoresist layer over the metal seed layer;   selectively patterning the photoresist layer to provide two or more openings that expose the metal seed layer through the photoresist layer;   electroplating to form two or more plate bumps from the metal seed layer exposed through the two or more openings, in which the metal seed layer works as an electroplating electrode for the two or more plate bumps so that an electrode wire does not have to be formed for each of the two or more plate bumps that would need to be removed after electroplating;   subsequent to electroplating, removing the photoresist layer to provide an intermediate structure comprising the substrate, the first insulating layer over the substrate, the metal seed layer over the first insulating layer and the two or more plate bumps that are on the metal seed layer with a horizontal gap therebetween;   subsequent to removing the photoresist layer, patterning the metal seed layer to form an intermediate device with the metal pattern comprising the electrical connection between the two or more plate bumps, wherein patterning the metal seed layer removes a portion of the conductive metal to expose the portion of the first insulating layer;   forming an insulating material over the intermediate device to provide the second insulating layer over the metal pattern and a third insulating layer over the portion of the first insulating layer, wherein forming the insulating material further forms a fourth insulating layer over the two or more plate bumps; and   removing the fourth insulating layer to expose a top portion of each of the two or more plate bumps.