Emission control driver and organic light emitting display device having the same

Abstract

An emission control driver includes stages sequentially outputting emission control signals through emission control lines. Each stage includes a first signal processor receiving a first voltage and generating first and second signals in response to first and second sub-control signals, a second signal processor receiving a second voltage having a level higher than a level of the first voltage and generating third and fourth signals in response to the third sub-control signal, the first signal, and the second signal, and a third signal processor receiving the first and second voltages and generating the emission control signal in response to the third and fourth signals. The first signal processor of each stage receives the emission control signal output from a previous stage as the first sub-control signal, and the first signal processor of a first stage among the stages receives a start signal as the first sub-control signal.

What is claimed is: 
     
       1. An emission control driver, comprising:
 a plurality of stages that sequentially outputs emission control signals through emission control lines, each stage including: 
 a first signal processing circuit that receives a first voltage and outputs first and second signals in response to first and second sub-control signals; 
 a second signal processing circuit that receives a second voltage having a level higher than a level of the first voltage and outputs third and fourth signals in response to a third sub-control signal, the first signal, and the second signal; and 
 a third signal processing circuit that receives the first and second voltages and outputs the emission control signal in response to the third and fourth signals, wherein: 
 the first signal processing circuit of a first stage among the stages receives a start signal as the first sub-control signal, 
 the first signal processing circuit of each stage except the first stage receives the emission control signal output from a previous stage as the first sub-control signal, 
 wherein: 
 the fourth signal changes from a second level to a third level at a time point at which the third sub-control signal changes from a first level to the second level, and 
 the fourth signal of the first stage changes from the second level to the first level at a time point at which the start second sub-control signal changes from the second first level to the first second level and the start signal is at the first level, the second level lower than the first level, and the third level lower than the second level. 
 
     
     
       2. The emission control driver as claimed in  claim 1 , wherein:
 the first signal processing circuit of each of odd-numbered stages of the stages receives a first clock signal as the second sub-control signal, 
 the second signal processing circuit of each of the odd-numbered stages of the stages receives a second clock signal as a third sub-control signal, 
 the first signal processing circuit of each of even-numbered stages of the stages receives the second clock signal as the second sub-control signal, and 
 the second signal processing circuit of each of the even-numbered stages of the stages receives the first clock signal as the third sub-control signal. 
 
     
     
       3. The emission control signal as claimed in  claim 2 , wherein the first and second clock signals have a same frequency and the second clock signal is obtained by shifting the first clock signal by a first duration corresponding to a half of a period of the first clock signal. 
     
     
       4. The emission control driver as claimed in  claim 3 , wherein the start signal is activated at a time point at which the first clock signal changes from the first level to the second level smaller than the first level, and the activation of the start signal is maintained during a second duration corresponding to four times of the first duration. 
     
     
       5. The emission control driver as claimed in  claim 3 , wherein each of the light emission control signals has the level of the second voltage during a third duration that is three times the first duration and the emission control signals are sequentially shifted by the first duration. 
     
     
       6. The emission control driver as claimed in  claim 2 , wherein the first signal processing circuit comprises:
 a first transistor having a gate terminal applied with the second sub-control signal and a first terminal applied with the first sub-control signal; 
 a second transistor having a gate terminal connected to a second terminal of the first transistor and a second terminal applied with the second sub-control signal; 
 a third transistor having a gate terminal applied with the second sub-control signal, a first terminal connected to a first terminal of the second transistor, and a second terminal applied with the first voltage, wherein 
 the first signal is output from the first terminals of the second and third transistors, which are connected to each other, and the second signal is output from the second terminal of the first transistor. 
 
     
     
       7. The emission control driver as claimed in  claim 6 , wherein the second signal processing circuit comprises:
 a fourth transistor having a gate terminal applied with the third sub-control signal and a second terminal connected to a first node and the second terminal of the first transistor 
 a first capacitor having a first electrode applied with the third sub-control signal and a second electrode connected to the second terminal of the fourth transistor; 
 a fifth transistor having a gate terminal connected to the first terminal of the third transistor and a second node, a first terminal applied with the second voltage, and a second terminal connected to a first terminal of the fourth transistor; 
 a sixth transistor having a gate terminal connected to the second node and a second terminal applied with the third sub-control signal; 
 a second capacitor having a first electrode connected to the gate terminal of the sixth transistor and a second electrode connected to a first terminal of the sixth transistor; and 
 a seventh transistor having a gate terminal applied with the third sub-control signal, a first terminal connected to a third node, and a second terminal connected to the first terminal of the sixth transistor, wherein the third signal is applied to the third node and the fourth signal is applied to the first node. 
 
     
     
       8. The emission control driver as claimed in  claim 7 , wherein the third signal processing circuit comprises:
 an eighth transistor having a gate terminal connected to the first node, a first terminal applied with the second voltage, and a second terminal connected to the third node; 
 a third capacitor having a first electrode applied with the second voltage and a second electrode connected to the third node; 
 a ninth transistor having a gate terminal connected to the third node, a first terminal applied with the second voltage, and a second terminal connected to a corresponding emission control line; and 
 a tenth transistor having a gate terminal connected to the first node, a first terminal connected to the corresponding emission control line, and a second terminal applied with the first voltage, wherein the second terminal of the ninth transistor and the first terminal of the tenth transistor are connected to a first terminal of a first transistor of a first signal processing circuit of a next stage. 
 
     
     
       9. An organic light emitting display device, comprising:
 a display panel that includes a plurality of pixels each being connected to a corresponding scan line of scan lines, a corresponding data line of data lines, and a corresponding emission control line of emission control lines; 
 a scan driver that sequentially applies scan signals to the pixels through the scan lines; 
 a data driver that applies data voltages to the pixels through the data lines; and 
 an emission control driver that includes a plurality of stages sequentially applying emission control signals to the pixels through the emission control lines, each of the stages including: 
 a first signal processing circuit that receives a first voltage and outputs first and second signals in response to first and second sub-control signals; 
 a second signal processing circuit that receives a second voltage having a level higher than a level of the first voltage and outputs third and fourth signals in response to a third sub-control signal, the first signal, and the second signal; and 
 a third signal processing circuit that receives the first and second voltages and outputs the emission control signal in response to the third and fourth signals, wherein: 
 the first signal processing circuit of a first stage among the stages receives a start signal as the first sub-control signal, 
 the first signal processing circuit of each stage except the first stage receives the emission control signal output from a previous stage as the first sub-control signal, 
 wherein: 
 the fourth signal changes from a second level to a third level at a time point at which the third sub-control signal changes from a first level to the second level, and 
 the fourth signal changes from the second level to the first level at a time point at which the start signal changes from the second level to the first level, the second level lower than the first level, and the third level lower than the second level. 
 
     
     
       10. The organic light emitting display device as claimed in  claim 9 , wherein:
 the first signal processing circuit of each of odd-numbered stages of the stages receives a first clock signal as the second sub-control signal, 
 the second signal processing circuit of each of the odd-numbered stages of the stages receives a second clock signal as a third sub-control signal, 
 the first signal processing circuit of each of even-numbered stages of the stages receives the second clock signal as the second sub-control signal, and 
 the second signal processing circuit of each of the even-numbered stages of the stages receives the first clock signal as the third sub-control signal. 
 
     
     
       11. The organic light emitting display device as claimed in  claim 10 , wherein:
 the first and second clock signals have a same frequency, 
 the second clock signal is obtained by shifting the first clock signal by a first duration corresponding to a half of a period of the first clock signal, and 
 the start signal is activated at a time point at which the first clock signal changes from the first level to the second level smaller than the first level, and 
 the activation of the start signal is maintained during a second duration that is four times the first duration. 
 
     
     
       12. The organic light emitting display device as claimed in  claim 11 , wherein the first signal processing circuit comprises:
 a first transistor having a gate terminal applied with the second sub-control signal and a first terminal applied with the first sub-control signal; 
 a second transistor having a gate terminal connected to a second terminal of the first transistor and a second terminal applied with the second sub-control signal; and 
 a third transistor having a gate terminal applied with the second sub-control signal, a first terminal connected to a first terminal of the second transistor, and a second terminal applied with the first voltage, wherein the first signal is output from the first terminals of the second and third transistors, which are connected to each other, and the second signal is output from the second terminal of the first transistor. 
 
     
     
       13. The organic light emitting display device as claimed in  claim 12 , wherein the second signal processing circuit comprises:
 a fourth transistor having a gate terminal applied with the third sub-control signal and a second terminal connected to a first node and the second terminal of the first transistor 
 a first capacitor having a first electrode applied with the third sub-control signal and a second electrode connected to the second terminal of the fourth transistor; 
 a fifth transistor having a gate terminal connected to the first terminal of the third transistor and a second node, a first terminal applied with the second voltage, and a second terminal connected to a first terminal of the fourth transistor; 
 a sixth transistor having a gate terminal connected to the second node and a second terminal applied with the third sub-control signal; 
 a second capacitor having a first electrode connected to the gate terminal of the sixth transistor and a second electrode connected to a first terminal of the sixth transistor; and 
 a seventh transistor having a gate terminal applied with the third sub-control signal, a first terminal connected to a third node, and a second terminal connected to the first terminal of the sixth transistor, wherein the third signal is applied to the third node, and the fourth signal is applied to the first node. 
 
     
     
       14. The organic light emitting display device as claimed in  claim 13 , wherein the third signal processing circuit comprises:
 an eighth transistor having a gate terminal connected to the first node, a first terminal applied with the second voltage, and a second terminal connected to the third node; 
 a third capacitor having a first electrode applied with the second voltage and a second electrode connected to the third node; 
 a ninth transistor having a gate terminal connected to the third node, a first terminal applied with the second voltage, and a second terminal connected to a corresponding emission control line; and 
 a tenth transistor having a gate terminal connected to the first node, a first terminal connected to the corresponding emission control line, and a second terminal applied with the first voltage, wherein the second terminal of the ninth transistor and the first terminal of the tenth transistor are connected to a first terminal of a first transistor of a first signal processing circuit of a next stage. 
 
     
     
       15. An emission control driver, comprising:
 a plurality of stages that sequentially outputs emission control signals through emission control lines, each stage including: 
 a bi-directional driver that outputs a first input signal or a second input signal as a first sub-control signal in response to a first direction control signal and a second direction control signal; 
 a first signal processing circuit that receives a first voltage and outputs a first signal and a second signal in response to the first sub-control signal and a second sub-control signal; 
 a second signal processing circuit that receives a second voltage having a level higher than a level of the first voltage and outputs a third signal and a fourth signal in response to a third sub-control signal, the first signal, and the second signal; and 
 a third signal processing circuit that receives the first voltage and the second voltage and outputs the emission control signal in response to the third signal and the fourth signal, wherein: 
 the bi-directional driver of a first stage among the stages receives a start signal as the first input signal, 
 the bi-directional driver of a last stage among the stages receives the start signal as the second input signal, 
 the bi-directional driver of each stage except the first stage receives the emission control signal output from a previous stage as the first input signal and the emission control signal output from a next stage as the second input signal, 
 wherein: 
 the fourth signal changes from a second level to a third level at a time point at which the third sub-control signal changes from a first level to the second level, and 
 the fourth signal changes from the second level to the first level at a time point at which the start signal changes from the second level to the first level, the second level lower than the first level, and the third level lower than the second level. 
 
     
     
       16. The emission control driver as claimed in  claim 15 , wherein the bi-directional driver applies the first input signal to the first signal processing circuit in response to the first direction control signal that is activated, and applies the second input signal to the first signal processing circuit in response to the second direction control signal that is activated. 
     
     
       17. The emission control driver as claimed in  claim 16 , wherein the bi-directional driver comprises:
 an eleventh transistor having a gate terminal applied with the first direction control signal and a first terminal applied with the first input signal; and 
 a twelfth transistor having a gate terminal applied with the second direction control signal, a first terminal applied with the second input signal, and a second terminal connected to a second terminal of the eleventh transistor, wherein the first sub-control signal is applied to the first signal processing circuit through the second terminals of the eleventh and twelfth transistors. 
 
     
     
       18. The emission control driver as claimed in  claim 15 , wherein:
 the first signal processing circuit of each of odd-numbered stages of the stages receives a first clock signal as the second sub-control signal, 
 the second signal processing circuit of each of the odd-numbered stages of the stages receives a second clock signal as a third sub-control signal, 
 the first signal processing circuit of each of even-numbered stages of the stages receives the second clock signal as the second sub-control signal, and 
 the second signal processing circuit of each of the even-numbered stages of the stages receives the first clock signal as the third sub-control signal. 
 
     
     
       19. The emission control driver as claimed in  claim 18 , wherein:
 the first and second clock signals have a same frequency, 
 the second clock signal is obtained by shifting the first clock signal by a first duration corresponding to a half of a period of the first clock signal, 
 the start signal is activated at a time point at which the first clock signal changes from the first level to the second level smaller than the first level, and 
 the activation of the start signal is maintained during a second duration corresponding to four times of the first duration. 
 
     
     
       20. The emission control driver as claimed in  claim 18 , wherein the first signal processing circuit comprises:
 a first transistor having a gate terminal applied with the second sub-control signal and a first terminal applied with the first sub-control signal; 
 a second transistor having a gate terminal connected to a second terminal of the first transistor and a second terminal applied with the second sub-control signal; and 
 a third transistor having a gate terminal applied with the second sub-control signal, a first terminal connected to a first terminal of the second transistor, and a second terminal applied with the first voltage, wherein the first signal is output from the first terminals of the second and third transistors, which are connected to each other, and the second signal is output from the second terminal of the first transistor. 
 
     
     
       21. The emission control driver as claimed in  claim 20 , wherein the second signal processing circuit comprises:
 a fourth transistor having a gate terminal applied with the third sub-control signal and a second terminal connected to a first node and the second terminal of the first transistor 
 a first capacitor having a first electrode applied with the third sub-control signal and a second electrode connected to the second terminal of the fourth transistor; 
 a fifth transistor having a gate terminal connected to the first terminal of the third transistor and a second node, a first terminal applied with the second voltage, and a second terminal connected to a first terminal of the fourth transistor; 
 a sixth transistor having a gate terminal connected to the second node and a second terminal applied with the third sub-control signal; 
 a second capacitor having a first electrode connected to the gate terminal of the sixth transistor and a second electrode connected to a first terminal of the sixth transistor; and 
 a seventh transistor having a gate terminal applied with the third sub-control signal, a first terminal connected to a third node, and a second terminal connected to the first terminal of the sixth transistor, wherein the third signal is applied to the third node, and the fourth signal is applied to the first node. 
 
     
     
       22. The emission control driver as claimed in  claim 21 , wherein the third signal processing circuit comprises:
 an eighth transistor having a gate terminal connected to the first node, a first terminal applied with the second voltage, and a second terminal connected to the third node; 
 a third capacitor having a first electrode applied with the second voltage and a second electrode connected to the third node; 
 a ninth transistor having a gate terminal connected to the third node, a first terminal applied with the second voltage, and a second terminal connected to a corresponding emission control line; and 
 a tenth transistor having a gate terminal connected to the first node, a first terminal connected to the corresponding emission control line, and a second terminal applied with the first voltage, wherein the second terminal of the ninth transistor and the first terminal of the tenth transistor are connected to a first terminal of a first transistor of a first signal processing circuit of a next stage. 
 
     
     
       23. An emission control driver, comprising:
 a plurality of stages that sequentially outputs emission control signals through emission control lines, each stage including: 
 a bi-directional driver that outputs a first input signal or a second input signal as a first sub-control signal in response to first and second direction control signals; 
 a first signal processing circuit that receives a first voltage and outputs first and a second signals in response to the first sub-control signal and a second sub-control signal; 
 a second signal processing circuit that receives a second voltage having a level higher than a level of the first voltage and outputs a third signal, a fourth signal, and a carry signal in response to a third sub-control signal, the first signal, and the second signal; and 
 a third signal processing circuit that receives the first and second voltages and outputs the emission control signal in response to the third and fourth signals, wherein: 
 the bi-directional driver of a first stage among the stages receives a start signal as the first input signal, 
 the bi-directional driver of a last stage among the stages receives the start signal as the second input signal, 
 the bi-directional driver of each stage except the first stage receives the carry signal output from a previous stage as the first input signal and the carry signal output from a next stage as the second input signal, 
 wherein: 
 the fourth signal changes from a second level to a third level at a time point at which the third sub-control signal changes from a first level to the second level, and 
 the fourth signal changes from the second level to the first level at a time point at which the start signal changes from the second level to the first level, the second level lower than the first level, and the third level lower than the second level. 
 
     
     
       24. The emission control driver as claimed in  claim 23 , wherein the bi-directional driver applies the first input signal to the first signal processing circuit in response to the first direction control signal that is activated, and applies the second input signal to the first signal processing circuit in response to the second direction control signal that is activated. 
     
     
       25. The emission control driver as claimed in  claim 24 , wherein the bi-directional driver comprises:
 an eleventh transistor having a gate terminal applied with the first direction control signal and a first terminal applied with the first input signal; and 
 a twelfth transistor having a gate terminal applied with the second direction control signal, a first terminal applied with the second input signal, and a second terminal connected to a second terminal of the eleventh transistor, wherein the first sub-control signal is applied to the first signal processing circuit through the second terminals of the eleventh and twelfth transistors. 
 
     
     
       26. The emission control driver as claimed in  claim 23 , wherein:
 the first signal processing circuit of each of odd-numbered stages of the stages receives a first clock signal as the second sub-control signal, 
 the second signal processing circuit of each of the odd-numbered stages of the stages receives a second clock signal as a third sub-control signal, 
 the first signal processing circuit of each of even-numbered stages of the stages receives the second clock signal as the second sub-control signal, and 
 the second signal processing circuit of each of the even-numbered stages of the stages receives the first clock signal as the third sub-control signal. 
 
     
     
       27. The emission control driver as claimed in  claim 26 , wherein:
 the first and second clock signals have a same frequency, 
 the second clock signal is obtained by shifting the first clock signal by a first duration corresponding to a half of a period of the first clock signal, 
 the start signal is activated at a time point at which the first clock signal changes from the first level to the second level smaller than the first level, and 
 the activation of the start signal is maintained during a second duration corresponding to four times of the first duration. 
 
     
     
       28. The emission control driver as claimed in  claim 26 , wherein the first signal processing circuit comprises:
 a first transistor having a gate terminal applied with the second sub-control signal and a first terminal applied with the first sub-control signal; 
 a second transistor having a gate terminal connected to a second terminal of the first transistor and a second terminal applied with the second sub-control signal; and 
 a third transistor having a gate terminal applied with the second sub-control signal, a first terminal connected to a first terminal of the second transistor, and a second terminal applied with the first voltage, wherein the first signal is output from the first terminals of the second and third transistors, which are connected to each other, and the second signal is output from the second terminal of the first transistor. 
 
     
     
       29. The emission control driver as claimed in  claim 28 , wherein the second signal processing circuit comprises:
 a fourth transistor having a gate terminal applied with the third sub-control signal and a second terminal connected to the first node and the second terminal of the first transistor; 
 a first capacitor having a first electrode connected to a fourth node and a second electrode connected to the second terminal of the fourth transistor; 
 a fifth transistor having a gate terminal connected to the first terminal of the third transistor and a second node, a first terminal applied with the second voltage, and a second terminal connected to a first terminal of the fourth transistor; 
 a sixth transistor having a gate terminal connected to the second node and a second terminal applied with the third sub-control signal; 
 a second capacitor having a first electrode connected to the gate terminal of the sixth transistor and a second electrode connected to a first terminal of the sixth transistor; 
 a seventh transistor having a gate terminal applied with the third sub-control signal, a first terminal connected to a third node, and a second terminal connected to the first terminal of the sixth transistor; 
 a thirteenth transistor having a gate terminal connected to the second node, a first terminal applied with the second voltage, and a second terminal connected to the fourth node; and 
 a fourteenth transistor having a gate terminal connected to the second electrode of the first capacitor, a first terminal connected to the fourth node, and a second terminal applied with the first second clock signal, wherein the third signal is applied to the third node, the fourth signal is applied to the first node, and a voltage at the fourth node is output as the carry signal. 
 
     
     
       30. The emission control driver as claimed in  claim 29 , wherein the third signal processing circuit comprises:
 an eighth transistor having a gate terminal connected to the first node, a first terminal applied with the second voltage, and a second terminal connected to the third node; 
 a third capacitor having a first electrode applied with the second voltage and a second electrode connected to the third node; 
 a ninth transistor having a gate terminal connected to the third node, a first terminal applied with the second voltage, and a second terminal connected to a corresponding emission control line; and 
 a tenth transistor having a gate terminal connected to the first node, a first terminal connected to the corresponding emission control line, and a second terminal applied with the first voltage, wherein the second terminal of the ninth transistor and the first terminal of the tenth transistor are connected to a first terminal of a first transistor of a first signal processing circuit of a next stage. 
 
     
     
       31. An emission control driver, comprising:
 a first voltage source;   a second voltage source having a voltage lower than a voltage of the first voltage source; and   a plurality of stages that sequentially output emission control signals through emission control lines, each of the stages comprising:
 a first transistor receiving a second sub-control signal and a first sub-control signal, the first transistor being controlled by the second sub-control signal; 
 a second transistor connected to the first voltage source and a corresponding one of the emission control lines; 
 a third transistor connected to the first transistor, the second transistor, and the second voltage source; 
 a first capacitor including a first electrode connected to the first transistor and a second electrode receiving a third sub-control signal; 
 a second capacitor connected to the first voltage source and the second transistor; and 
 a fourth transistor connected to the second transistor, the third transistor, and the first voltage source, 
   wherein the corresponding one of the emission control lines is connected between the second transistor and the third transistor, and   wherein the first transistor of each of the stages except a first one of the stages receives the emission control signal output from a previous stage as the first sub-control signal.   
     
     
       32. The emission control driver of claim 31, wherein the third transistor is controlled by three voltage levels. 
     
     
       33. The emission control driver of claim 31, wherein each of the stages further comprises:
 a third capacitor connected to the second transistor and receiving the second sub-control signal.   
     
     
       34. The emission control driver of claim 33, wherein each of the stages further comprises:
 a fifth transistor connected to the third capacitor and receiving the third sub-control signal.   
     
     
       35. The emission control driver of claim 34, wherein each of the stages further comprises:
 a sixth transistor connected to the third capacitor and the first transistor, and receiving the second sub-control signal; and   a seventh transistor connected to the third capacitor and the second voltage source, receiving the second sub-control signal, and controlled by the second sub-control signal.   
     
     
       36. The emission control driver of claim 32, wherein each of the stages further comprises:
 a third capacitor connected the second transistor and receiving the second sub-control signal.   
     
     
       37. The emission control driver of claim 36, wherein each of the stages further comprises:
 a fifth transistor connected to the third capacitor and receiving the third sub-control signal.   
     
     
       38. The emission control driver of claim 37, wherein each of the stages further comprises:
 a sixth transistor connected to the third capacitor and the first transistor, and receiving the second sub-control signal; and   a seventh transistor connected to the third capacitor and the second voltage source, receiving the second sub-control signal, and controlled by the second sub-control signal.