Semiconductor integrated circuit

Abstract

Disclosed herein is a semiconductor integrated circuit, wherein a desired circuit is formed by combining and laying out a plurality of standard cells and connecting the cells together, of which the cell length, i.e., the gap between a pair of opposed sides, is standardized, the plurality of standard cells forming the desired circuit include complementary in-phase driven standard cells, each of which includes a plurality of complementary transistor pairs that are complementary in conductivity type to each other and have their gate electrodes connected together, and N (≥2) pairs of all the complementary transistor pairs are driven in phase, and the size of the standardized cell length of the complementary in-phase driven standard cell is defined as an M-fold cell length which is M (N≥M≥2) times the basic cell length which is appropriate to the single complementary transistor pair.

What is claimed is: 
     
       1. A semiconductor integrated circuit, wherein
 a desired circuit is formed by combining and laying out plurality of standard cells and connecting the cells together, of which the cell length, i.e., the gap between a pair of opposed sides, is standardized,   the plurality of standard cells forming the desired circuit include complementary in-phase driven standard cells, each of which includes a plurality of complementary transistor pairs that are complementary in conductivity type to each other and have their gate electrodes connected together, and N (≥2) pairs of all the complementary transistor pairs are driven in phase, and   the size of the standardized cell length of the complementary in-phase driven standard cell is defined as an M-fold cell length which is M (N≥M≥2) times the basic cell length which is appropriate to the single complementary transistor pair, and the common gate electrodes of at least M pairs of the N complementary transistor pairs to be driven in phase are arranged linearly in the direction of the M-fold cell length.   
     
     
       2. The semiconductor integrated circuit of  claim 1 , wherein
 single height cells or standard cells having the basic cell length and multi-height cells or the complementary in-phase driven standard cells having the M-fold cell length are arranged adjacent to each other to share power lines so as to form the desired circuit.   
     
     
       3. The semiconductor integrated circuit of  claim 2 , wherein
 the multi-height cell has a total of (M+1) power lines which is the sum of (M−1) power wirings that are arranged parallel to each other to extend in an arbitrary cell length direction orthogonal to the M-fold cell length with a separation pitch equal to the basic cell length obtained by dividing the M-fold cell length into M equal parts and two shared power wirings, each of which is shared with an adjacent cell at the center of the width of one of two cell boundaries, one on each side along the M-fold cell length,   the (M+1) power lines include source voltage lines and reference voltage lines that are alternately arranged, and   the single height cell connected to a pair of the source voltage line and reference voltage line arranged adjacent and parallel to each other is arranged adjacent to the multi-height cell in the arbitrary cell length direction.   
     
     
       4. The semiconductor integrated circuit of  claim 3 , wherein
 two active regions of the same conductivity type where transistors are respectively formed are arranged line-symmetrically with respect to the center line of the width of each of the (M−1) power wirings, and   the common gate electrodes are arranged linearly to intersect each of one of the active regions, power wirings and the other of the active regions.   
     
     
       5. The semiconductor integrated circuit of  claim 4 , wherein
 all the gate electrodes overlapping an element isolation region provided between the two active regions are the common gate electrodes extending from one of the two active regions to the other of the two active regions and intersecting the element isolation region.   
     
     
       6. The semiconductor integrated circuit of  claim 3 , wherein
 the (M+1) power lines and all intracell connection lines are formed with a first metal wiring layer, and   intercell signal lines are formed with a second metal wiring layer.   
     
     
       7. The semiconductor integrated circuit of  claim 2 , wherein
 the multi-height cell is a non-rectangular cell that surrounds the single height cell in an L-shaped manner by including first and second rectangular sections, the first rectangular section having the M-fold cell length in which M complementary transistor pairs of all the complementary transistor pairs to be driven in phase are arranged, and the second rectangular section extending along one of two sides that are opposed to each other in the direction of the standardized cell length of the first rectangular section.   
     
     
       8. The semiconductor integrated circuit of  claim 1 , wherein
 a plurality of standard cells forming the desired circuit include at least one non-rectangular standard cell that is L-shaped as a whole in plan view by comprising first and second rectangular sections, the first rectangular section having the M-fold cell length in which M complementary transistor pairs of all the complementary transistor pairs to be driven in phase are arranged, and the second rectangular section extending along one of two sides that are opposed to each other in the direction of the standardized cell length of the first rectangular section.   
     
     
       9. A semiconductor integrated circuit comprising:
 first voltage lines that extend in a first direction, the first direction differs from a second direction;   second voltage lines that extend in the first direction, one of the second voltage lines is between one of the first voltage lines and a different one of the first voltage lines;   a first active region of a first conductivity type, the first conductivity type differs from a second conductivity type;   a second active region of the second conductivity type, the first active region and the second active region are between the one of the first voltage lines and the one of the second voltage lines:   a third active region of the first conductivity type that an element isolation region isolates from the first active region and the second active region;   a fourth active region of the second conductivity type that the element isolation region isolates from the second active region and the third active region, the third active region and the fourth active region are between the one of the second voltage lines and the different one of the first voltage lines;   a first gate electrode configured to drive a plurality of complementary transistor pairs, the first gate electrode extends along the second direction to overlap at least the first active region and the second active region and the third active region and the fourth active region; and   a second gate electrode configured to drive a plurality of complementary transistor pairs, the second gate electrode extends along the second direction to overlap at least the first active region and the second active region and the third active region and the fourth active region.   
     
     
       10. A semiconductor integrated circuit as set forth in claim 9, further comprising:
 a fifth active region of the first conductivity type that the element isolation region isolates from the first active region and the second active region and the third active region and the fourth active region, the first gate electrode and the second gate electrode extend along the second direction to overlap the fifth active region.   
     
     
       11. A semiconductor integrated circuit as set forth in claim 9, wherein the third active region continuously extends in the first direction. 
     
     
       12. A semiconductor integrated circuit as set forth in claim 9, wherein the first gate electrode has a straight linear shape. 
     
     
       13. A semiconductor integrated circuit as set forth in claim 9, wherein the first gate electrode intersects with the one of the second voltage lines. 
     
     
       14. A semiconductor integrated circuit as set forth in claim 9, wherein the first gate electrode is configured to drive at least part of a first logic circuit and at least part of a second logic circuit, a function the second logic circuit differs from a function of the first logic circuit. 
     
     
       15. A semiconductor integrated circuit as set forth in claim 14, wherein the first logic circuit is NAND circuit, and the second circuit is an inverter circuit. 
     
     
       16. A semiconductor integrated circuit as set forth in claim 9, wherein the first gate electrode is configured to drive a plurality of complementary transistor pairs, the second gate electrode is configured to drive another plurality of the complementary transistor pairs. 
     
     
       17. A semiconductor integrated circuit as set forth in claim 9, wherein the second gate electrode has a straight linear shape. 
     
     
       18. A semiconductor integrated circuit as set forth in claim 9, wherein the second gate electrode intersects with the one of the second voltage lines. 
     
     
       19. A semiconductor integrated circuit as set forth in claim 9, wherein the first gate electrode and the second gate electrode are formed from the electrically conductive material. 
     
     
       20. A semiconductor integrated circuit as set forth in claim 9, wherein a length of the first gate electrode is same as a length of the second gate electrode. 
     
     
       21. A semiconductor integrated circuit as set forth in claim 9, wherein the second gate electrode is adjacent to the first gate electrode. 
     
     
       22. A semiconductor integrated circuit as set forth in claim 9, wherein the first gate electrode is configured to drive a plurality of inverters, the second gate electrode is configured to drive another plurality of the inverters. 
     
     
       23. A semiconductor integrated circuit as set forth in claim 10, further comprising:
 a sixth active region of the second conductivity type that the element isolation region isolates from the first active region and the second active region and the third active region and the fourth active region and the fifth active region.   
     
     
       24. A semiconductor integrated circuit as set forth in claim 23, wherein the fifth active region and the sixth active region are between the one of the first voltage lines and a different one of the second voltage lines, the first gate electrode extends along the second direction while overlapping at least the fifth active region and the sixth active region. 
     
     
       25. A semiconductor integrated circuit as set forth in claim 24, wherein one of the first voltage lines is between the one of the second voltage lines and the different one of the second voltage lines. 
     
     
       26. A semiconductor integrated circuit as set forth in claim 9, wherein the first gate electrode and the second gate electrode extend in a multi-height standard cell, a cell length of the multi-height standard cell is an integral multiple of a cell length of a single height standard cell. 
     
     
       27. A semiconductor integrated circuit as set forth in claim 26, further comprising:
 a transistor in the multi-height standard cell, wiring is connected to a source region of the transistor or a drain region of the transistor.   
     
     
       28. A semiconductor integrated circuit as set forth in claim 27, wherein a first layer includes the wiring. 
     
     
       29. A semiconductor integrated circuit as set forth in claim 28, wherein the wiring crosses the one of the second voltage lines at an intersection point, the one of the second voltage lines is physically isolated from the wiring at the intersection point. 
     
     
       30. A semiconductor integrated circuit as set forth in claim 28, wherein a second layer includes the first voltage lines and the second voltage lines. 
     
     
       31. A semiconductor integrated circuit as set forth in claim 30, wherein a gate layer, the first layer and the second layer are arranged in order. 
     
     
       32. A semiconductor integrated circuit as set forth in claim 30, wherein a gate layer is under the first layer, the gate layer is under the second layer.