Computing device and method using associative pattern memory using recognition codes for input patterns

Abstract

Pattern recognition based on associative pattern memory (APM) and properties of cycles generated by finite cellular automata. APM addresses (e.g., positions in a two dimensional array) represent states. Cycles are repeating sequences of addresses. Each state is mapped to a “randomly” selected region within the input pattern. Each feature extracted from this region determines one of many next states. All next states (one for each feature type) and all sampled regions are assigned to each state randomly upon APM initialization. The process progresses from state to state, sampling regions of the pattern until the state-transition sequence repeats (generates a cycle). Each feature pattern is represented by one cycle, however different cycles can be derived from one pattern depending on the initial state. Some embodiments use a refractory period assuring a minimum cycle length, making it likely that any given pattern yields only one cycle independent of the initial state.

What is claimed is: 
     
       1. An apparatus comprising:
 a memory having an address space; 
 a lower-level recognition unit that generating, for a first set of input patterns loaded into a first lower-level-input-pattern portion of the memory, generates a first set of paths of addresses, 
 wherein the first set of paths of addresses includes a first path for a first pattern in the first set of input patterns and a second path for a second pattern in the first set of input patterns, 
 wherein each respective one path of the first set of paths of addresses has a respective series of addresses in the address space based on its corresponding respective an input pattern from the first set of input patterns, 
 wherein the lower-level recognition unit outputs generates a first set of recognition codes pattern identifiers for the first set of input patterns based on the first set of paths of addresses, and 
 wherein the first set of recognition codes pattern identifiers are loaded as at least part of a first upper-level pattern into an upper-level-pattern portion of the memory; and 
 aan upper-level recognition unit thatgenerating, forfrom the first set of recognition codespattern identifiers loaded as the first upper-level pattern into the upper-level-pattern portion of the memory, generates a third path of addresses, 
 wherein the third path of addresses has a series of addresses in the address space that are based on the first upper-level pattern, and 
 wherein the upper-level recognition unit outputs a first upper-level recognition code pattern identifier for the first set of input patterns based on the third path of addresses. 
 
     
     
       2. The apparatus of  claim 1 , wherein the lower-level recognition unit further includes:
 a cycle-detection unit that detects detecting when each path of the first set of paths forms a cycle that repeats addresses in its path; 
 a vertical sensor system that generates generating a lower-level path hash code for each respective cycle, wherein the lower-level path hash code includes a plurality of bits, wherein each bit of the lower-level path hash code corresponds to a corresponding plurality of addresses in the address space, and wherein each of the respective bits of the lower-level path hash code is set based on whether the respective cycle includes one of the plurality of addresses corresponding to the bit; and 
 a first response recognition table for the lower-level path hash code, wherein the first response recognition table includes one of a plurality of recognition codes pattern identifiers in each of a plurality of addressed locations in the first response recognition table, and wherein the lower-level path hash code is used to address the first response recognition table uses the lower-level path hash code as an address and outputs to obtain the respective recognition code pattern identifier from the addressed location indicated by the address addressed by the lower-level path hash code. 
 
     
     
       3. The apparatus of  claim 2 , wherein the pattern identifiers in the first response recognition table is configured to generate recognition codes are based on audio input patterns, and wherein the upper-level recognition unit is configured to output generate a recognition code pattern identifier based on a plurality of audio input patterns. 
     
     
       4. The apparatus of  claim 2 , wherein the pattern identifiers in the first response recognition table is configured to generate recognition codes are based on video input patterns, and wherein the upper-level recognition unit is configured to output generate a recognition code pattern identifier based on a plurality of image input patterns. 
     
     
       5. The apparatus of  claim 1 , wherein the lower-level recognition unit further includes:
 a cycle-detection unit that detects detecting when each path of the first set of paths forms a cycle that repeats addresses in its path; 
 a vertical sensor system that generates generating a plurality of lower-level path hash codes for each respective cycle, wherein each one of the plurality of lower-level path hash codes includes a plurality of bits, wherein each bit of each lower-level path hash code corresponds to a corresponding plurality of addresses in the address space, and wherein, for each respective cycle, each of the respective bits of each of the plurality of lower-level path hash codes is set based on whether the respective cycle includes one of the plurality of addresses corresponding to the bit; 
 a plurality of lower-level response recognition tables that includes a respective response recognition table for each respective one of the plurality of lower-level path hash codes, wherein each one of a plurality of addressed locations in each one of the plurality of lower-level response recognition tables includes one of a plurality of lower-level recognition codes pattern identifiers, and wherein each one of the plurality of lower-level response recognition tables uses is addressed using its lower-level path hash code as an address and outputs to obtain the respective lower-level recognition code pattern identifier from the addressed location indicated by the address; and 
 a fuzzy recognition unit that receives receiving the outputted lower-level recognition codes pattern identifiers from the plurality of lower-level response recognition tables and that generates a fuzzy recognition based on the lower-level recognition codes pattern identifiers. 
 
     
     
       6. The apparatus of  claim 1 , wherein the lower-level recognition unit further includes:
 a trace-detection unit that detects detecting when each path of the first set of paths forms a path trace that includes a predetermined number of address steps such that the path would eventually end up in a looping pattern that repeats addresses in its path; 
 a vertical sensor system that generates generating a lower-level path hash code for each respective path trace, wherein the lower-level path hash code includes a plurality of bits, wherein each bit of the lower-level path hash code corresponds to a corresponding plurality of addresses in the address space, and wherein each of the respective bits of the lower-level path hash code is set based on whether the respective path trace includes one of the plurality of addresses corresponding to the bit; and 
 a first response recognition table for the lower-level path hash code, wherein the first response recognition table includes one of a plurality of recognition codes pattern identifiers in each of a plurality of addressed locations in the first response recognition table, and wherein the lower-level path hash code is used to address the first response recognition table uses the lower-level path hash code as an address and outputs to obtain the respective recognition code pattern identifier from the addressed location indicated by the address addressed by the lower-level path hash code. 
 
     
     
       7. The apparatus of  claim 6 , wherein the pattern identifiers in the first response recognition table is configured to generate recognition codes are based on audio input patterns, and wherein the upper-level recognition unit is configured to output generate an audio-pattern recognition code pattern identifier based on a plurality of audio input patterns. 
     
     
       8. The apparatus of  claim 6 , wherein the pattern identifiers in the first response recognition table is configured to generate recognition codes are based on video input patterns, and wherein the upper-level recognition unit is configured to output a generate an image-pattern recognition code pattern identifier based on a plurality of image input patterns. 
     
     
       9. The apparatus of claim  1  22, wherein the first pattern in the first set of input pattern patterns is also loaded as at least part of the first upper-level pattern in the upper-level-pattern portion of the memory, and wherein the third path is based on the first upper-level pattern having data from both the first pattern in the first set of input pattern patterns and the first set of recognition codes pattern identifiers. 
     
     
       10. The apparatus of  claim 1 , wherein the lower-level recognition unit and the upper-level recognition unit are configured to perform recursive recognition. 
     
     
       11. A computerized method comprising:
 providing a memory having an address space; 
 loading a first set of input patterns into a first lower-level-input-pattern portion of the memory, wherein the first set of input patterns includes a first pattern and a second pattern; 
 generating, for the first set of input patterns loaded into the first lower-level-input-pattern portion of the memory, a first set of paths of addresses, 
 wherein the first set of paths of addresses includes a first path for the first pattern and a second path for the second pattern, 
 wherein each respective one path of the first set of paths of addresses has a respective series of addresses in the address space based on its corresponding respective an input pattern from the first set of input patterns, 
 forming a first set of recognition codes pattern identifiers for the first set of input patterns based on the first set of paths of addresses, wherein the first set of recognition codes pattern identifiers are loaded as at least part of a first upper-level pattern into an upper-level-pattern portion of the memory; and  
 generating, for the first set of recognition codes pattern identifiers loaded as the first upper-level pattern into the upper-level-pattern portion of the memory, a third path of addresses, wherein the third path of addresses has a series of addresses in the address space that are based on the first upper-level pattern; and 
 outputting a first upper-level recognition code pattern identifiers for the first set of input patterns based on the third cycle of addresses. 
 
     
     
       12. The method of  claim 11 , further comprising:
 loading each of a plurality of addressed locations in a lower-level response recognition table with a respective one of a plurality of recognition codes pattern identifiers; 
 detecting when each path of the first set of paths forms a cycle that repeats addresses in its path; 
 generating a lower-level path hash code for each respective cycle in the first set of paths, wherein the lower-level path hash code includes a plurality of bits, wherein each bit of the lower-level path hash code corresponds to a corresponding plurality of addresses in the address space, and wherein each of the respective bits of the lower-level path hash code is set based on whether the respective cycle includes one of the plurality of addresses corresponding to the bit; and 
 using the lower-level path hash code as an address into the lower-level response recognition table and outputting obtaining, from the lower-level response recognition table, the respective recognition code pattern identifier from the addressed location indicated by the address. 
 
     
     
       13. The method of  claim 12 , wherein the pattern identifiers in the first response recognition table is configured to generate recognition codes are based on audio input patterns, and wherein the upper-level recognition unit is configured to output generate a recognition code pattern identifier based on a plurality of audio input patterns. 
     
     
       14. The method of  claim 12 , wherein the pattern identifiers in the first response recognition table is configured to generate recognition codes are based on video input patterns, and wherein the upper-level recognition unit is configured to output generate a recognition code pattern identifier based on a plurality of image input patterns. 
     
     
       15. The method of  claim 11 , further including:
 loading each of a plurality of addressed locations in a plurality of lower-level response recognition tables with a respective one of a plurality of recognition codes pattern identifiers; 
 detecting when each path of the first set of paths forms a cycle that repeats addresses in its path; 
 generating a plurality of lower-level path hash codes for each respective cycle, wherein each one of the plurality of lower-level path hash codes includes a plurality of bits, wherein each bit of each lower-level path hash code corresponds to a corresponding plurality of addresses in the address space, and wherein each of the respective bits of the plurality of lower-level path hash codes is set based on whether the respective cycle includes one of the plurality of addresses corresponding to the bit; and 
 using each one of the plurality of lower-level path hash codes as an address into a respective one of the plurality of lower-level response recognition tables and outputting obtaining, from each respective one of the plurality of lower-level response recognition tables, the respective recognition code pattern identifier from the addressed location indicated by the address. 
 
     
     
       16. The method of  claim 11 , further including:
 loading each of a plurality of addressed locations in a lower-level response recognition table with a respective one of a plurality of recognition codes pattern identifiers; 
 detecting when each path of the first set of paths forms a path cycle that repeats addresses in its path; 
 generating a lower-level path hash code for each respective path cycle, wherein the lower-level path hash code includes a plurality of bits, wherein each bit of the lower-level path hash code corresponds to a corresponding plurality of addresses in the address space, and wherein each of the respective bits of the lower-level path hash code is set based on whether the respective cycle includes one of the plurality of addresses corresponding to the bit; and 
 using the lower-level path hash code from each cycle as an address into the lower-level response recognition table and outputting obtaining, the respective recognition code pattern identifier for each cycle from the addressed location indicated by the respective address. 
 
     
     
       17. The method of  claim 16 , wherein the pattern identifiers in the lower-level response recognition table is configured to generate recognition codes are based on audio input patterns, and wherein the upper-level recognition unit is configured to output generate an audio-pattern recognition code pattern identifier based on a plurality of audio input patterns. 
     
     
       18. The method of  claim 16 , wherein the pattern identifiers in the lower-level response recognition table is configured to generate recognition codes are based on video input patterns, and wherein the upper-level recognition unit is configured to output a generate an image-pattern recognition code pattern identifier based on a plurality of image input patterns. 
     
     
       19. The method of claim  11  24, further comprising loading the first pattern in the first set of input pattern patterns into the upper-level-pattern portion of the memory as at least part of the first upper-level pattern, and wherein the third path is based on the first upper-level pattern having data from both the first pattern in the first set of input pattern patterns and the first set of recognition codes pattern identifiers. 
     
     
       20. An apparatus comprising:
 a memory having an address space; 
 means for loading a first set of input patterns into a first lower-level-input-pattern portion of the memory, wherein the first set of input patterns includes a first pattern and a second pattern; 
 means for generating, for the first set of input patterns loaded into the first lower-level-input-pattern portion of the memory, a first set of paths of addresses, 
 wherein the first set of paths of addresses includes a first path for the first pattern and a second path for the second pattern, 
 wherein each respective one of the first set of paths of addresses has a respective series of addresses in the address space based on its corresponding respective input pattern; 
 means for forming a first set of recognition codes pattern identifiers for the first set of input patterns based on the first set of paths of addresses, 
 means for loading the first set of recognition codes pattern identifiers as at least part of a first upper-level pattern into an upper-level-pattern portion of the memory; 
 means for generating, for the first set of recognition codes pattern identifiers loaded as the first upper-level pattern into the upper-level-pattern portion of the memory, a third path of addresses, wherein the third path of addresses has a series of addresses in the address space that are based on the first upper-level pattern; and 
 means for outputting generating a first upper-level recognition code pattern identifier for the first set of input patterns based on the third cycle of addresses. 
 
     
     
       21. The apparatus of claim 1, wherein the first set of paths of addresses includes a first path for a first pattern in the first set of input patterns and a second path for a second pattern in the first set of input patterns.  
     
     
       22. The apparatus of claim 21, wherein:
 the upper-level recognition unit generates a third path of addresses for the first set of pattern identifiers loaded as the first upper-level pattern into the upper-level-pattern portion of the memory, wherein the third path of addresses has a series of addresses in the address space that are based on the first upper-level pattern; and   the first upper-level pattern identifier for the first set of input patterns is based on the third path of addresses.    
     
     
       23. The method of claim 11, wherein the first set of input patterns includes a first pattern and a second pattern and wherein the first set of paths of addresses includes a first path for the first pattern and a second path for the second pattern.  
     
     
       24. The method of claim 23, wherein generating a first upper-level pattern identifier comprises generating a third path of addresses, wherein the third path of addresses has a series of addresses in the address space that are based on the first upper-level pattern, and the first upper-level pattern identifier is based on the third path of addresses.