Memory system having high data transfer efficiency and host controller

Abstract

According to one embodiment, the host controller includes a register set to issue command, and a direct memory access (DMA) unit and accesses a system memory and a device. First, second, third and fourth descriptors are stored in the system memory. The first descriptor includes a set of a plurality of pointers indicating a plurality of second descriptors. Each of the second descriptors comprises the third descriptor and fourth descriptor. The third descriptor includes a command number, etc. The fourth descriptor includes information indicating addresses and sizes of a plurality of data arranged in the system memory. The DMA unit sets, in the register set, the contents of the third descriptor forming the second descriptor, from the head of the first descriptor as a start point, and transfers data between the system memory and the host controller in accordance with the contents of the fourth descriptor.

What is claimed is: 
     
       1. A host controller which is connected to a memory device through an interface, accesses a system memory, and is controlled by a CPU executing a host driver, wherein each of first, second, third, and fourth descriptors has an attribute field for identifying a type of the descriptors, and designating a processing method of the descriptors, the host controller comprising:
 a register set which is configured to store a part of information in the third descriptor; 
 a command controller which is configured to issue a command to the memory device according to the information stored in the register set; and 
 a direct memory access (DMA) unit which is configured to load the first, third, and fourth descriptors into the host controller, and is configured to transfer data between the system memory and the memory device according to the first, second, third, and fourth descriptors, 
 wherein the first descriptor includes a plurality of pointers to the second descriptors with attributes, 
 the second descriptor includes the third descriptor and the fourth descriptor,  
 each of the pointers of the first descriptor indicates a leading region of the third descriptor, 
 the third descriptor includes command issue information and attributes, 
 the fourth descriptor includes a number of DMA execution information and attributes, and 
 the first descriptor, the second descriptor, the third descriptor, and the fourth descriptor have a hierarchical structure,  
 wherein the DMA unit is configured (1) to load the first descriptor, (2) to acquire the pointer from the loaded first descriptor, (3) to load the second descriptor including the third descriptor and the fourth descriptor based on the acquired pointer, (4) to execute a data transfer between the system memory and the memory device, (5) to repeat the process of (2) to (4) until the attribute of the first descriptor indicates the end of descriptor, and (6) to generate an interrupt to the CPU when the data transfer is end ended or during a DMA data transfer, 
 wherein the third descriptors descriptor includes information to generate a data transfer command of the memory device, a command argument, a command number, a block length, and the number of blocks, 
 wherein the fourth descriptor includes information to designate system memory areas addresses, and sizes for each of a plurality of scattered data in the system memory, and 
 wherein the DMA unit includes: 
 a system address controller configured to control addresses of the system memory pointing data and each descriptor, and 
 a data buffer, 
 wherein the data in the system memory is read to the data buffer in accordance with the fourth descriptor, and the data in the data buffer is transferred to the memory device in accordance with the third descriptor when the data is written into the memory device, and 
 the data in the memory device is read to the data buffer in accordance with the third descriptor, and the data in the data buffer is transferred to the system memory in accordance with the fourth descriptor when the data is read from the memory device. 
 
     
     
       2. The host controller according to  claim 1 , wherein the fourth descriptor is programmed so that a sum of sizes of a plurality of scattered data equals to the block length indicated in the third descriptor. 
     
     
       3. The host controller according to  claim 1 , wherein the data transfer between the host controller and the memory device is started by a memory read/write command which is issued by command controller when setting information of the third descriptor to the register set is completed, and
 the memory device acquires information necessary for the data transfer from the command. 
 
     
     
       4. A method for transferring data between a memory device and a system memory executed by a host controller, the system memory storing first, second, third, and fourth descriptors, the method comprising:
 (1) loading the first descriptor including a plurality of pointers with attributes; 
 (2) acquiring a pointer to the second descriptor from the loaded first descriptor, wherein the pointer indicates a leading region of the third descriptor, wherein the second descriptor includes the third descriptor and the fourth descriptor; 
 (3) loading the third descriptor included in the second descriptor based on the pointer to issue a command, wherein the third descriptor includes command issue information and attributes; 
 (4) issuing a command according to the loaded third descriptor; 
 (5) loading the fourth descriptor included in the second descriptor based on the pointer, wherein the fourth descriptor includes a number of DMA execution information and attributes, wherein the first descriptor, the second descriptor, the third descriptor, and the fourth descriptor have a hierarchical structure; 
 (6) when the issued command is a read-command, reading data from the system memory to a data buffer in accordance with the fourth descriptor and transferring the data from the data buffer to the memory device in accordance with the third descriptor; 
 when the issued command is a write-command, reading data from the memory device to the data buffer in accordance with the third descriptor, and transferring the data from the data buffer to the system memory in accordance with the fourth descriptor; 
 (7) repeating (2) to (6) until an attribute of the first descriptor indicates the end of descriptor; and 
 (8) generating an interrupt when a data transfer is end ended or during a DMA data transfer, 
 wherein the third descriptor includes information to generate a data transfer command of the memory device, a command argument, a command number, a block length, and the number of blocks, 
 wherein the fourth descriptor includes information to designate system memory areas addresses, and sizes for each of a plurality of scattered data in the system memory. 
 
     
     
       5. The method according to  claim 4 , wherein the first, third, and fourth descriptors includes:
 information for indicating the type of descriptor; and 
 an end bit indicating the last descriptor for each of the first, third, and fourth descriptors. 
 
     
     
       6. A method for transferring data between a memory device and a system memory executed by a host controller, the system memory storing first, second, third, and fourth descriptors, the method comprising:
 (1) loading the first descriptor including a plurality of pointers with attributes;   (2) acquiring a pointer to the second descriptor from the loaded first descriptor, wherein the second descriptor includes the third descriptor and the fourth descriptor, and wherein the pointer indicates a leading region of the third descriptor;   (3) loading the second descriptor including the third descriptor and the fourth descriptor based on the acquired pointer, wherein the third descriptor includes command issue information and attributes, and the fourth descriptor includes a number of DMA execution information and attributes, wherein the first descriptor, third descriptor, and the fourth descriptor have a hierarchical structure;   (4) executing a data transfer between the system memory and the memory device in accordance with the loaded third descriptor and the loaded fourth descriptor,   (5) repeating (2) to (4) until the attribute of the first descriptor indicates the end of descriptor, and   (6) generating an interrupt when the data transfer is ended or during a DMA data transfer,   wherein the third descriptor includes information to generate a data transfer command of the memory device, a command argument, a command number, a block length, and the number of blocks; and   wherein the fourth descriptor includes information to designate system memory areas addresses, and sizes for each of a plurality of scattered data in the system memory.    
     
     
       7. The method according to claim 6, wherein (4) includes:
 when the data is transferred to the memory device,
 storing data from the system memory in a data buffer; and 
 restoring the data to write the data to the memory device, and 
   when the data is transferred to the system memory,
 storing data from the memory device in the data buffer; and 
 restoring the data to write the data to the system memory.  
   
     
     
       8. The method according to claim 6, further comprising:
 issuing a memory read/write command to start the data transfer between the host controller and the memory device,   wherein the memory device acquires information necessary for the data transfer from the command.