Semiconductor device and method of forming electrical interconnect with stress relief void

Abstract

A semiconductor device has a semiconductor die with a plurality of tapered bumps formed over a surface of the semiconductor die. The tapered bumps can have a non-collapsible portion and collapsible portion. A plurality of conductive traces is formed over a substrate with interconnect sites. A masking layer is formed over the substrate with openings over the conductive traces. The tapered bumps are bonded to the interconnect sites so that the tapered bumps contact the mask layer and conductive traces to form a void within the opening of the mask layer over the substrate. The substrate can be non-wettable to aid with forming the void in the opening of the masking layer. The void provides thermally induced stress relief. Alternatively, the masking layer is sufficiently thin to avoid the tapered interconnect structures contacting the mask layer. An encapsulant or underfill material is deposited between the semiconductor die and substrate.

What is claimed: 
     
       1. A method of making a semiconductor device, comprising:
 providing a semiconductor die including a plurality of elongated bumps formed over a metallization on a surface of the semiconductor die, wherein a length of the elongated bumps parallel to the surface of the semiconductor die is greater than a width of the elongated bumps parallel to the surface of the semiconductor die; 
 providing a substrate; 
 forming a plurality of conductive traces over the substrate and radially oriented toward a geometric center of the semiconductor die; 
 bonding the elongated bumps to the interconnect site of the conductive traces so that with the length of the elongated bumps include a width across taken in a direction along the conductive traces less than a length along greater than the width of the elongated bumps taken in a direction across the conductive traces; and 
 depositing an encapsulant around the elongated bumps between the semiconductor die and substrate. 
 
     
     
       2. The method of  claim 1 , wherein a width of the bump elongated bumps across a surface of the metallization on the semiconductor die is 1.5 to 4.0 times the width of the bump elongated bumps across the conductive traces. 
     
     
       3. The method of  claim 1 , wherein the elongated bumps include a non-collapsible portion and collapsible portion. 
     
     
       4. The method of  claim 3 , wherein the non-collapsible portion of the elongated bumps includes gold, copper, nickel, lead solder, or lead-tin alloy and the collapsible portion of the elongated bumps includes tin, lead-free alloy, tin-silver alloy, tin-silver-copper alloy, tin-silver-indium alloy, eutectic solder, or tin alloys including silver, copper, or lead. 
     
     
       5. The method of  claim 1 , wherein the substrate is non-wettable along portions of the traces to limit flow of the elongated bumps. 
     
     
       6. A method of making a semiconductor device, comprising:
 providing a semiconductor die including a plurality of elongated interconnect structures on a surface of the semiconductor die, wherein a length of the elongated interconnect structures parallel to the surface of the semiconductor die is greater than a width of the elongated interconnect structures parallel to the surface of the semiconductor die; 
 providing a substrate; 
 forming a plurality of conductive traces over the substrate and radially oriented toward a geometric center of the semiconductor die; 
 forming a plurality ofbonding the semiconductor die to the substrate with the elongated interconnect structures between the semiconductor die andcontacting the conductive traces so that the interconnect structures include a length along the conductive tracesand the length of the elongated interconnect structures taken in a direction along the conductive traces greater than the width of the elongated interconnect structures taken in a direction across the conductive traces; and 
 depositing an encapsulant between the semiconductor die and substrate. 
 
     
     
       7. The method of  claim 6 , wherein a width of the elongated interconnect structures across a surface of the semiconductor die is 1.5 to 4.0 times a width of the elongated interconnect structures across the conductive traces. 
     
     
       8. The method of  claim 6 , wherein the elongated interconnect structures include a non-collapsible portion and collapsible portion. 
     
     
       9. The method of  claim 8 , wherein the non-collapsible portion of the elongated interconnect structures includes gold, copper, nickel, lead solder, or lead-tin alloy and the collapsible portion of the elongated interconnect structures includes tin, lead-free alloy, tin-silver alloy, tin-silver-copper alloy, tin-silver-indium alloy, eutectic solder, or tin alloys comprising copper or lead. 
     
     
       10. The method of  claim 6 , wherein the elongated interconnect structures cover a top surface and side surface of the conductive traces. 
     
     
       11. The method of  claim 6 , wherein the elongated interconnect structures diffuse strain away from the semiconductor die. 
     
     
       12. The method of  claim 6 , wherein the interconnect structures include a width across the conductive traces less than the length along the conductive traces. 
     
     
       13. A method of making a semiconductor device, comprising:
 providing a semiconductor die including a plurality of interconnect structures on a surface of the semiconductor die, wherein a length of the interconnect structures parallel to the surface of the semiconductor die is greater than a width of the interconnect structures parallel to the surface of the semiconductor die; 
 providing a substrate; 
 forming a plurality of conductive traces over the substrate and oriented toward a geometric center of the semiconductor die; and 
 forming adisposing the plurality of interconnect structures between the semiconductor die and the conductive traces and in contact with the conductive traces, wherein the length of the interconnect structures taken in a direction along the conductive traces is greater than the width of the interconnect structures taken in a direction across the conductive traces. 
 
     
     
       14. The method of  claim 13 , further including depositing an encapsulant or underfill material between the semiconductor die and substrate using a mold underfill (MUF) process. 
     
     
       15. The method of  claim 13 , wherein the interconnect structures include a width across the conductive traces less than a length along the conductive traces. 
     
     
       16. The method of  claim 13 , wherein the interconnect structures include a non-collapsible portion and collapsible portion. 
     
     
       17. The method of  claim 13 , wherein the interconnect structures include a conductive pillar and bump formed over the conductive pillar. 
     
     
       18. The method of  claim 13 , wherein a width of the interconnect structures across a surface of the semiconductor die is 1.5 to 4.0 times a the width of the interconnect structures across the conductive traces. 
     
     
       19. A semiconductor device, comprising:
 a semiconductor die including a plurality of interconnect structures formed on a surface of the semiconductor die, wherein a length of the interconnect structures parallel to the surface of the semiconductor die is greater than a width of the interconnect structures parallel to the surface of the semiconductor die; 
 a substrate including a plurality of conductive traces formed over the substrate; 
 a, wherein the plurality of interconnect structures is formed between the semiconductor die and the conductive traces and including a length along the conductive traces oriented toward a geometric center of the semiconductor die, and the length of the interconnect structures taken in a direction along the conductive traces is greater than the width of the interconnect structures taken in a direction across the conductive traces; and 
 an encapsulant deposited between the semiconductor die and substrate. 
 
     
     
       20. The semiconductor device of  claim 19 , wherein the interconnect structures include a width across the conductive traces less than a length along the conductive traces. 
     
     
       21. The semiconductor device of  claim 19 , wherein the interconnect structures include a non-collapsible portion and collapsible portion. 
     
     
       22. The semiconductor device of  claim 21 , wherein the non-collapsible portion of the interconnect structures includes gold, copper, nickel, lead solder, or lead-tin alloy and the collapsible portion of the interconnect structures includes tin, lead-free alloy, tin-silver alloy, tin-silver-copper alloy, tin-silver-indium alloy, eutectic solder, or tin alloys comprising copper or lead. 
     
     
       23. The semiconductor device of  claim 19 , wherein the interconnect structures include a conductive pillar and bump disposed over the conductive pillar. 
     
     
       24. The semiconductor device of  claim 19 , wherein a width of the interconnect structures across a surface of the semiconductor die is 1.5 to 4.0 times a the width of the interconnect structures across the conductive traces. 
     
     
       25. A semiconductor device, comprising:
 a substrate; 
 a semiconductor component disposed over the substrate; and 
 a conductive trace formed over the substrate and including an orientation towards a thermally neutral point of the semiconductor component; and 
 an elongated interconnect structure formed between the semiconductor component and an interconnect site of the conductive trace, wherein a length of the elongated interconnect structure taken in a direction along the interconnect site is greater than a width of the elongated interconnect structure taken in a direction across the interconnect site, and the width of the elongated interconnect structure is tapered along the length of the elongated interconnect structure to be wider proximate to the semiconductor component and narrower proximate to the interconnect site. 
 
     
     
       26. The semiconductor device of  claim 25 , wherein the orientation of the conductive trace deviates less than forty five degrees from being directly aligned towards the thermally neutral point of the semiconductor component. 
     
     
       27. The semiconductor device of  claim 25 , further including an interconnect structure connected between the conductive trace and the semiconductor component. 
     
     
       28. The semiconductor device of claim  27  25, further including a portion of the elongated interconnect structure collapsed around covers a top surface and side surface of the conductive trace. 
     
     
       29. The semiconductor device of  claim 27 , wherein the interconnect structure further includes a length along the conductive trace and a width across the conductive trace less than the length along the conductive trace. 
     
     
       30. The semiconductor device of claim  27  25, wherein a width of the elongated interconnect structure across a surface of the semiconductor component is 1.5 to 4.0 times a the width of the elongated interconnect structure across the conductive trace. 
     
     
       31. The semiconductor device of claim 1, wherein the width of the elongated bumps is tapered along the length of the elongated bumps to be wider proximate to the semiconductor die and narrower proximate to the conductive traces. 
     
     
       32. The semiconductor device of claim 6, wherein the width of the elongated interconnect structures is tapered along the length of the elongated interconnect structures to be wider proximate to the semiconductor die and narrower proximate to the conductive traces. 
     
     
       33. The semiconductor device of claim 13, wherein the width of the interconnect structures is tapered along the length of the interconnect structures to be wider proximate to the semiconductor die and narrower proximate to the conductive traces. 
     
     
       34. The semiconductor device of claim 19, wherein the width of the interconnect structures is tapered along the length of the interconnect structures to be wider proximate to the semiconductor die and narrower proximate to the conductive traces.