Silicon on insulator and thin film transistor bandgap engineered split gate memory

Abstract

Memory cells comprising thin film transistor, stacked arrays, employing bandgap engineered tunneling layers in a junction free, NAND configuration. The cells comprise a channel region in a semiconductor strip formed on an insulating layer; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising a multilayer structure including at least one layer having a hole-tunneling barrier height lower than that at the interface with the channel region; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer Arrays and methods of operation are described.

What is claimed is: 
     
       1. A method for forming a semiconductor structure, comprising:
 forming a plurality of first parallel semiconductor body regions bodies with a first dopant type over a substrate; 
 forming a plurality of first parallel word lines between a first select line and a second select line, the first word lines, the first select line and the second select line being over and intersecting the first semiconductor body regions bodies in an array of cross points; 
 forming a first tunneling barrier, a first charge storage layer and a first dielectric layer between the first semiconductor body regions bodies and the first word lines; 
 forming first dielectric spacers on a sidewall of the first select line and a sidewall of the second select line; 
 forming first source/drain (S/D) junctions with a second dopant type adjacent to the first select line and the second select line; 
 forming a second dielectric layer over the first word lines; 
 forming a plurality of second parallel semiconductor body regions bodies with the first dopant type over the second dielectric layer; 
 forming a plurality of second parallel word lines between a third select line and a fourth select line, the second parallel word lines, the third select line and the fourth select line being over and substantially perpendicular to the second semiconductor body regions bodies; 
 forming a second tunneling barrier, a second charge storage layer and a third dielectric layer between the second semiconductor body regions bodies and the second word lines; 
 forming second dielectric spacers on a sidewall of the third select line and a sidewall of the fourth select line; and 
 forming second source/drain (S/D) regions junctions with the second dopant type adjacent to the third select line and the fourth select line; 
 wherein the regions in the first semiconductor body regions bodies between two neighboring first word lines and the regions in the second semiconductorbody regions bodies between two neighboring second word lines are junction-free. 
 
     
     
       2. The method of  claim 1 , wherein forming the first dielectric spacers includes forming first dielectric materials between two neighboring first word lines. 
     
     
       3. The method of  claim 1 , wherein forming the first source/drain (S/D) regions junctions includes using the first dielectric spacers as an implantation mask. 
     
     
       4. The method of  claim 1 , further comprising forming a plurality of trench structures adjacent to and parallel with the first semiconductor body regions bodies. 
     
     
       5. The method of  claim 1 , wherein forming the S/D first source/drain (S/D) junctions comprises:
 forming a patterned mask layer overlying at least portions of the first and second select lines and the first word lines; and 
 implanting dopants of the second dopant type into the first semiconductor body regions bodies by using the patterned mask layer as an implantation mask. 
 
     
     
       6. The method of  claim 1 , wherein forming the first tunneling barrier comprises forming a tunnel dielectric structure having multilayer or composite composition with a first hole tunneling barrier height at an interface interfaces with the first semiconductor body bodies, and a second hole tunneling barrier height spaced away from the interface interfaces that is less than the first hole tunneling barrier height at the interface interfaces. 
     
     
       7. The method of  claim 1 , further comprising forming an oxide layer between the substrate and the first semiconductor body regions bodies. 
     
     
       8. The method of  claim 1 , wherein forming the second dielectric spacers includes forming a second dielectric material between two neighboring second word lines. 
     
     
       9. The method of  claim 1 , wherein forming the second source/drain (S/D) regions junctions includes using the second dielectric spacers as an implantation mask. 
     
     
       10. The method of  claim 1 , wherein forming the first S/D regions source/drain (S/D) junctions comprises implanting dopants with the second dopant type into the first semiconductor body regions bodies by using first dielectric materials as an implantation stop layer so as to prevent implanting the dopants within the first semiconductor body regions bodies between two neighboring first word lines. 
     
     
       11. The method of  claim 1 , wherein the method does not include an implantation process for forming common source/drain regions (S/D) junctions within the first semiconductor body regions bodies between the first word lines. 
     
     
       12. A method for forming a semiconductor structure, comprising:
 forming a plurality of first semiconductor body regions bodies; 
 forming a plurality of first word lines, each of the plurality of first word lines overlying crossing over a channel region in each of the first semiconductor body regions bodies; 
 forming a first tunneling barrier, a first charge storage layer, and a first dielectric layer between each of the first word lines and a corresponding channel region in each of the first semiconductor body regions bodies, wherein regions in the first semiconductor body regions bodies between one of the first word lines and another one of the first word lines are junction-free; 
 forming an inter-dielectric layer over the first word lines; 
 forming a plurality of second semiconductor body regions bodies overlying the inter-dielectric layer; 
 forming a plurality of second word lines over crossing over channel regions in each of the second semiconductor body regions bodies; and 
 forming a second tunneling barrier, a second charge storage layer and a second dielectric layer between the second word lines and a corresponding channel region in each of the second semiconductor body region bodies. 
 
     
     
       13. A memory device, comprising:
 a first gate and a second gate;   a first semiconductor body including a first channel surface and a second semiconductor body including a second channel surface;   a first tunnel structure and a first charge storage region located between the first gate and the first channel surface;   the first tunnel structure including a first portion and second portion, a middle portion located between the first and second portion, the first portion having a valence band energy, the middle portion having a valence band energy greater than that of the first portion, the second portion having a valence band energy less than that of the middle portion; and   a second tunnel structure and a second charge storage region located between the second gate and the second channel surface, wherein the first charge storage region is over the second charge storage region.   
     
     
       14. The memory device of claim 13, wherein the first and second gates include a material having a work function greater than that of N+ polysilicon. 
     
     
       15. A method of forming a memory device, comprising:
 forming a first plurality of gates;   forming a first semiconductor body;   forming a first plurality of multi-layered hole-tunneling dielectrics and a first plurality of charge storage regions between the first plurality of gates and the first semiconductor body;   forming a second plurality of gates;   forming a second semiconductor body; and   forming a second plurality of multi-layered hole-tunneling dielectrics and a second plurality of charge storage regions between the second plurality of gates and the second semiconductor body, wherein a semiconductor region between one of the second gates and another one of the second gates is junction-free and the first plurality of charge storage regions are over the second plurality of charge storage regions.   
     
     
       16. The method of forming a memory device of claim 15, wherein a semiconductor region between one of the first gates and another one of the first gates is junction-free. 
     
     
       17. The method of forming a memory device of claim 16, wherein the first and second plurality of gates include a material having a work function greater than that of N+ polysilicon. 
     
     
       18. The method of forming a memory device of claim 16, wherein both the first and the second plurality of multi-layered hole-tunneling dielectrics include a first portion and second portion, a middle portion located between the first and second portion, the first portion having a valence band energy, the middle portion having a valence band energy greater than that of the first portion, the second portion having a valence band energy less than that of the middle portion.