Cell structure for dual-port SRAM

Abstract

The present disclosure provides a dual port static random access memory (SRAM) cell. The dual-port SRAM cell includes a first and second inverters cross-coupled for data storage, each inverter includes a pull-up device (PU) and a plurality of pull-down devices (PDs); a plurality of pass gate devices configured with the two cross-coupled inverters; and at least two ports coupled with the plurality of pass gate devices (PGs) for reading and writing, wherein each of PU, PDs and PGs includes a fin field-effect transistor (FinFET), a ratio between a number of PDs in the SRAM cell and a number of PGs in the SRAM cell is greater than 1, and a number of FinFETs in the SRAM cell is equal to or greater than 12.

What is claimed is: 
     
       1. A static random access memory (SRAM) cell comprising:
 first and second inverters cross-coupled for data storage, each inverter including a pull-up device (PU) and a plurality of pull-down devices (PDs);   a plurality of pass gate devices (PGs) configured with the two cross-coupled inverters; and   at least two ports coupled with the plurality of PGs for writing, wherein:
 each of the PU, PDs, and PGs includes a fin field-effect transistor (FinFET), 
 a ratio between a number of PDs in the first and second inverters and a number of PGs in the at least two ports is greater than 1, 
 a number of FinFETs in the SRAM cell is equal to or greater than 12; 
   a first metal layer providing local interconnection to the first and second inverters, the first metal layer including:
 a first Vss line and a second Vss line; 
 a Vdd line; 
 a first constant voltage line and a second constant voltage line; and 
 a first bit line and a second bit line, wherein the first and second Vss lines, the Vdd line, the first and second constant voltage lines, and the first and second bit lines are oriented in a first direction; 
   a second metal layer formed over the first metal layer, the second metal layer including a first word line and a second word line oriented in a second direction that is different from the first direction, wherein the first word line is a write word line and the second word line is a read word line; and   a read port for reading, wherein the read port is different than the at least two ports coupled with the plurality of PGs for writing, wherein the read port includes at least two PDs in parallel and at least two PGs in parallel.   
     
     
       2. The SRAM cell of  claim 1 , wherein each FinFET includes a channel having a top portion with a first width and a sidewall portion with a second width, the first width being less than the second width. 
     
     
       3. The SRAM cell of  claim 1 , further comprising a plurality of FinFETs formed on a plurality of fin-type active regions. 
     
     
       4. The SRAM cell of  claim 1 , wherein the ratio is equal to one of 3/2 and 5/4. 
     
     
       5. The SRAM cell of  claim 1 , further comprising at least four pass-gate devices, at least six pull-down devices, and at least two pull-up devices. 
     
     
       6. The SRAM cell of  claim 5 , comprising:
 a first PU (PU 1 ), a first PD (PD 11 ), a second PD (PD 12 ), and a third PD (PD 13 ) configured to form the first inverter, wherein drains of PU 1 , PD 11 , PD 12 , and PD 13  are electrically connected to form a first drain node;   a second PU (PU 2 ), a fourth PD (PD 21 ), a fifth PD (PD 22 ), and a sixth PD (PD 23 ) configured to form the second inverter, wherein drains of PU 2 , PD 21 , PD 22 , and PD 23  are electrically connected to form a second drain node;   a first PG (PG 1 ) and second PG (PG 2 ) configured to form a first port, wherein:
 a first drain of PG 1  is electrically connected to a bit-line of the first port, 
 a second drain of PG 2  is electrically connected to a bit-line bar of the first port, 
 a first source of PG 1  is electrically connected to the first drain node, and 
 a second source of PG 2  is electrically connected to the second drain node; and 
   a third PG (PG 3 ) and fourth PG (PG 4 ) configured to form a second port, wherein:
 a third drain of PG 3  is electrically connected to a bit-line of the second port, 
 a fourth drain of PG 4  is electrically connected to a bit-line bar of the second port, 
 a third source of PG 3  is electrically connected to the first drain node, and 
 a fourth source of PG 4  is electrically connected to the second drain node. 
   
     
     
       7. The SRAM cell of  claim 1 , wherein at least one of the first and second constant voltage lines is configured between the first and second bit lines for noise shielding, and wherein the first and second constant voltage lines are electrically connected to Vdd and Vss. 
     
     
       8. A static random access memory (SRAM) cell comprising:
 a first set of fin field-effect transistors (FinFETs) having two pull-up devices (PUs) and a first number of pull-down devices (PDs) configured to form first and second cross-coupled inverters;   a second set of FinFETs having a second number of pass-gate devices (PGs) configured to form at least two ports, wherein the first number is greater than the second number;   word lines connected to gates of the PGs, respectively;   bit lines connected to drains of the PGs, respectively,   two Vss lines and a Vdd line, wherein the two Vss lines, the Vdd line, and the bit lines are formed in a first metal layer and oriented in a first direction, and the word lines are formed in a second metal layer over the first metal layer and oriented in a second direction different from the first direction, the word lines comprise a write word line and a read word line; and   a read port that is different than the at least two ports, wherein the read port includes at least two PDs in parallel and at least two PGs in parallel.   
     
     
       9. The SRAM cell of  claim 8 , wherein the first set and second set of FinFETs include at least 12 FinFETs. 
     
     
       10. The SRAM cell of  claim 8 , wherein a ratio between the first number and the second number is equal to one of 3:2, 2:1, or 5:4. 
     
     
       11. The SRAM cell of  claim 8 , wherein the first and second sets of FinFETs are formed on a plurality of fin active regions. 
     
     
       12. The SRAM cell of  claim 8 , wherein
 the first inverter includes a first subset of the PDs, wherein drains of the first set of the PDs are electrically connected together through one of silicide, long contact line, and combinations thereof; and   the second inverter includes a second subset of the PDs, wherein drains of the second set of the PDs are electrically connected together through one of silicide, long contact line, and combination thereof.   
     
     
       13. The SRAM cell of  claim 8 , wherein a ratio between a first length of the word lines and a second length of the bit lines is greater than about 3.5:1. 
     
     
       14. The SRAM cell of  claim 8 , wherein at least one of the Vdd line and the Vss lines is configured between two bit-lines for noise shielding. 
     
     
       15. The SRAM cell of  claim 8 , further comprising at least four Vss lines. 
     
     
       16. A dual port static random access memory (SRAM) cell comprising:
 a first inverter having a first pull-up transistor (PU 1 ) and a first group of pull-down transistors (PDs);   a second inverter having a second pull-up transistor (PU 2 ) and a second group of PDs, the second inverter being cross-coupled with the first inverter;   a first group of pass-gate transistors (PGs) coupled with the first and second inverters to form a first port; and   a second group of PGs coupled with the first and second inverters to form a second port;   wherein each of the PDs and PGs includes an n-type fin field-effect transistor (nFinFET) and each of the pull-up transistors includes a p-type fin field-effect transistor (pFinFET), and wherein there are more PDs than PGs in the SRAM cell;   a first metal layer providing local interconnection to the first and second inverters, the first metal layer including:
 a first Vss line and a second Vss line; 
 a Vdd line positioned between the first and second Vss lines; 
 a first constant voltage line and a second constant voltage line; and 
 a first bit line and a second bit line, wherein the first and second Vss lines, the Vdd line, the first and second constant voltage lines, and the first and second bit lines are oriented in a first direction; 
   a second metal layer formed over the first metal layer, the second metal layer including a first word line and a second word line oriented in a second direction that is different from the first direction, wherein the first word line is a write word line and the second word line is a read word line; and   a read port that is different than the first and second ports, wherein the read port includes at least two PDs in parallel and at least two PGs in parallel.   
     
     
       17. The SRAM cell of  claim 16 , wherein
 the first group of PDs includes 5 nFinFETs, wherein drains of the first group of PDs are connected through one of silicide and long contact line;   the second group of PDs includes 5 nFinFETs, wherein drains of the second group of PDs are connected through one of silicide and long contact line;   the first group of PGs includes 4 nFinFETs; and   the second group of PGs includes 4 nFinFETs.   
     
     
       18. The SRAM cell of  claim 16 , wherein
 the first group of PDs includes PD 11 , PD 12 , and PD 13 ;   the second group of PDs includes PD 21 , PD 22 , and PD 23 ;   the first group of PGs includes PG 1  and PG 2 ;   the second group of PGs includes PG 3  and PG 4 ; and   wherein the PD 12  and PG 1  are formed in a first continuous fin active region, and the PD 22  and PG 4  are formed in a second continuous fin active region.   
     
     
       19. The SRAM cell of  claim 16 , wherein:
 the first group of PDs includes 6 nFinFETs formed on first four long fin active regions and first two short fin active regions;   the second group of PDs includes 6 nFinFETs formed on second four long fin active regions and second two short fin active regions;   the first group of PGs includes 4 nFinFETs;   the second group of PGs includes 4 nFinFETs; and   wherein each of the first and second groups of PGs is formed on one of the first and second four long fin active regions.   
     
     
       20. The SRAM cell of  claim 16 , wherein:
 the first group of PDs includes 4 nFinFETs formed on two fin active regions;   the second group of PDs includes 4 nFinFETs formed on another two fin active regions;   the first group of PGs includes PG 1  and PG 2 ;   the second group of PGs includes PG 3  and PG 4 ; and   wherein the PG 1  and PG 3  are formed in a first continuous fin active region, and the PG 2  and PG 4  are formed in a second continuous fin active region.   
     
     
       21. A static random access memory (SRAM) cell including a plurality of pass gate fin field-effect transistor (FINFET), a plurality of pull-down FINFET, and a plurality of pull-up FINFET, the SRAM cell comprising:
 a first fin and a second fin on a semiconductor substrate in a first well region, wherein each of the first and second fins includes source, channel, and drain regions of one of the pull-up FINFETs;   a third fin and a fourth fin on the semiconductor substrate in a second well region, wherein each of the third and fourth fins includes source, channel, and drain regions of one of the pull-down FINFETs and one of the third and fourth fins further includes source, channel, and drain regions of one of the pass gate FINFETs, wherein the third and fourth fins are spaced apart from a first side of the first and second fins;   a fifth fin and a sixth fin on the semiconductor substrate in the second well region, wherein each of the fifth and sixth fins includes source, channel, and drain regions of one of the pull-down FINFETs and one of the fifth and sixth fins further includes source, channel, and drain regions of one of the pass gate FINFETs, wherein the fifth and sixth fins are spaced apart from a second side opposite to the first side of the first and second fins;   wherein the first, second, third, fourth, fifth, and sixth fins extend in a first direction;   a first gate layer formed on at least one of the first and second fins and at least one of the third and fourth fins, wherein the first gate layer includes gate regions of at least one of the pull-down FINFETs and at least one of pull-up FINFETs;   a second gate layer formed on at least one the first and second fins and at least one of the fifth and sixth fins, wherein the second gate layer includes gate regions of at least one of the pull-down FINFETs and at least one of pull-up FINFETs;   a third gate layer formed on at least one of the third and fourth fins, wherein the third gate layer includes gate regions of at least one of the pass gate FINFETs;   a fourth gate layer formed on at least one of the fifth and sixth fins, wherein the fourth gate layer includes gate regions of at least one of the pass gate FINFETs;   wherein the first, second, third and fourth gate layers extend in a second direction perpendicular to the first direction;   a first contact feature formed on the third and fourth fins between the first and third gate layers, wherein the first contact feature extends in the second direction;   a second contact feature formed on the first fin for connecting the first contact feature with the second gate layer, wherein the second contact feature extends in the first direction;   a third contact feature formed on the fifth and sixth fins between the second and fourth gate layers, wherein the third contact feature extends in the second direction;   a fourth contact feature formed on the second fin for connecting the third contact feature with the first gate layer, wherein the fourth contact feature extends in the first direction; and   a read port that includes at least two pull-down FINFETs in parallel and at least two pass gate FINFETs in parallel.   
     
     
       22. The SRAM cell of claim 21, wherein the first well region is one of a n-well region and a p-well region and the second well region is another one of the n-well region and the p-well region. 
     
     
       23. The SRAM cell of claim 21, wherein the first gate layer is formed on the first fin and the second gate layer is formed on the second fin. 
     
     
       24. The SRAM cell of claim 21, wherein, along the second direction, each of the contact features has a dimension greater than a dimension of the fin where the respective contact feature is formed on. 
     
     
       25. The SRAM cell of claim 21, further comprising:
 a fifth contact feature on the first fin for connecting to a first power line;   a sixth contact feature on the second fin for connecting to the first power line;   a seventh contact feature on the third and fourth fins for connecting to a second power line; and   an eighth contact feature on the fifth and sixth fins for connecting to the second power line.   
     
     
       26. The SRAM cell of claim 25, wherein the first power line connects to one of VCC and VSS and the second power line connects to another one of VCC and VSS. 
     
     
       27. The SRAM cell of claim 25, further comprising:
 a ninth contact feature on at least one of the third and fourth fins for connecting to a first bit line; and   a tenth contact feature on at least one of the fifth and sixth fins for connecting to a second bit line.   
     
     
       28. The SRAM cell of claim 27, further comprising:
 an eleventh contact feature on the third gate layer for connecting to a first word line; and   a twelfth contact feature on the fourth gate layer for connecting to a second word line.   
     
     
       29. The SRAM cell of claim 28, further comprising:
 a seventh fin on the semiconductor substrate in the second well region, wherein the seventh fin includes source, channel, and drain regions of one of the pass gate FINFETs and wherein the third gate layer is formed on the seventh fin; and   an eighth fin on the semiconductor substrate in the second well region, wherein the eighth fin includes source, channel, and drain regions of one of the pass gate FINFETs and wherein the fourth gate layer is formed on the eighth fin,   wherein the seventh and eighth fins extend in the first direction.   
     
     
       30. The SRAM cell of claim 29, further comprising:
 a thirteenth contact feature on the seventh fin for connecting to the first gate layer;   a fourteenth contact feature on the eighth fin for connecting to the second gate layer;   a fifteenth contact feature on the seventh fin for connecting to a third bit line; and   a sixteenth contact feature on the eighth fin for connecting to a fourth bit line.   
     
     
       31. The SRAM cell of claim 30, wherein the first and third bit lines are complementary bit lines and the second and fourth bit lines are complementary bit lines. 
     
     
       32. The SRAM cell of claim 21, further comprising:
 a first common region on at least one of the third and fourth fins defined by the source and drain regions of one of the pull down FINFETs and one of the pass gate FINFETs connected in series therethrough; and   a second common region on at least one of the fifth and sixth fins defined by the source and drain regions of one of the pull down FINFETs and one of the pass gate FINFETs connected in series therethrough.   
     
     
       33. The SRAM cell of claim 32, wherein the first contact feature is formed on the first common region and the second contact feature is formed on the second common region. 
     
     
       34. A static random access memory (SRAM) cell including a plurality of pass gate fin field-effect transistors (FINFETs), a plurality of pull-down FINFETs, and a plurality of pull-up FINFETs, the SRAM cell comprising:
 a first fin on a semiconductor substrate in an n-well region;   second, third, fourth, and fifth fins on the semiconductor substrate in a p-well region and on one side of the first fin;   a sixth fin on the semiconductor substrate in the n-well region and on another side of the first fin;   seventh, eighth, ninth, and tenth fins on the semiconductor substrate in another p-well region, wherein the first fin and the seventh through tenth fins are on opposite sides of the sixth fin, wherein the first through tenth fins are distributed along a first direction and oriented along a second direction that is perpendicular to the first direction;   wherein the first fin includes source, channel, and drain regions of a first pull-up FINFET;   wherein the second, third, and fourth fins include source, channel, and drain regions of first, second, third pull-down FINFETs respectively;   wherein the third fin further includes source, channel, and drain regions of a first pass gate FINFET, wherein the drain region of the second pull-down device and the source region of the first pass gate device share a first common region in the third fin;   wherein the fifth fin includes source, channel, and drain regions of a second pass gate FINFET;   wherein the sixth fin includes source, channel, and drain regions of a second pull-up FINFET;   wherein the seventh, eighth, and ninth fins include source, channel, and drain regions of fourth, fifth, and sixth pull-down FINFETs respectively, and the eighth fin further includes source, channel, and drain regions of a third pass gate FINFET, wherein the drain region of the fifth pull-down FINFET and the source region of the third pass gate FINFET share a second common region in the eighth fin;   wherein the tenth fin includes source, channel, and drain regions of a fourth pass gate FINFET;   a first contact feature that electrically connects to at least the first common region and the drain region of the first pull-up FINFET;   a second contact feature that electrically connects to at least the second common region and the drain region of the second pull-up FINFET; and   a read port that includes at least two pull-down FINFETs in parallel and at least two pass gate FINFETs in parallel.   
     
     
       35. The SRAM cell of claim 34, further comprising:
 a first gate electrode oriented in the first direction and over the channel regions of the first pull-up FINFET and the first, second, and third pull-down FINFETs;   a second gate electrode oriented in the first direction and over the channel regions of the second pull-up FINFET and the fourth, fifth, and sixth pull-down FINFETs;   a third gate electrode oriented in the first direction and over the channel regions of the first and second pass gate FINFETs; and   a fourth gate electrode oriented in the first direction and over the channel regions of the third and fourth pass gate FINFETs.   
     
     
       36. The SRAM cell of claim 35, further comprising:
 a third contact feature that electrically connects the source region of the first pull-up FINFET to a first power line;   a fourth contact feature that electrically connects the source regions of the first, second, and third pull-down FINFETs to a second power line;   a fifth contact feature that electrically connects the drain region of the first pass gate FINFET to a first bit line;   a sixth contact feature that electrically connects the drain region of the second pass gate FINFET to a second bit line;   a seventh contact feature that electrically connects the third gate electrode to a first word line;   a eighth contact feature that electrically connects the source region of the second pull-up FINFET to the first power line;   a ninth contact feature that electrically connects the source regions of the fourth, fifth, and sixth pull-down FINFETs to the second power line;   a tenth contact feature that electrically connects the drain region of the third pass gate FINFET to a third bit line;   a eleventh contact feature that electrically connects the drain region of the fourth pass gate FINFET to a fourth bit line; and   a twelfth contact feature that electrically connects the fourth gate electrode to a second word line.   
     
     
       37. The SRAM cell of claim 35, further comprising:
 a third contact feature that electrically connects to the first contact feature and the second gate electrode, wherein the first and third contact features form an L-shape.   
     
     
       38. The SRAM cell of claim 37, wherein the first and third contact features and the second gate electrode are in a same interconnect level of the SRAM cell. 
     
     
       39. The SRAM cell of claim 37, further comprising:
 a fourth contact feature that electrically connects to the second contact feature and the first gate electrode, wherein the second and fourth contact features form an L-shape.   
     
     
       40. The SRAM cell of claim 39, wherein the second and fourth contact features and the first gate electrode are in a same interconnect level of the SRAM cell. 
     
     
       41. The SRAM cell of claim 35, further comprising:
 a first conductive feature that electrically connects to the source region of the second pass gate FINFET and the first gate electrode; and   a second conductive feature that electrically connects to the source region of the fourth pass gate FINFET and the second gate electrode.   
     
     
       42. The SRAM cell of claim 41, wherein the first and second conductive features and the first and second gate electrode are in a same interconnect level of the SRAM cell. 
     
     
       43. The SRAM cell of claim 35, wherein the first gate electrode lands on the source region of the second pass gate FINFET, and the second gate electrode lands on the source region of the fourth pass gate FINFET. 
     
     
       44. A dual port static random access memory (SRAM) cell including a plurality of pass gate fin field-effect transistor (FINFETs), a plurality of pull-down FINFETs, and a plurality of pull-up FINFETs, the SRAM cell comprising:
 a first fin on a semiconductor substrate in an n-well region;   second, third, fourth, and fifth fins on the semiconductor substrate in a p-well region on one side of the n-well region;   a sixth fin on the semiconductor substrate in the n-well region;   seventh, eighth, ninth, and tenth fins on the semiconductor substrate in another p-well region on another side of the n-well region, wherein the first through tenth fins are distributed along a first direction and oriented along a second direction that is perpendicular to the first direction;   wherein the first and sixth fins include source, channel, and drain regions of first and second pull-up FINFETs;   wherein the second, third, and fourth fins include source, channel, and drain regions of first, second, and third pull-down FINFETs respectively;   wherein the third fin further includes source, channel, and drain regions of a first pass gate FINFET, wherein the drain region of the second pull-down FINFET and the source region of the first pass gate FINFET share a first common region in the third fin;   wherein the fifth fin includes source, channel, and drain regions of a second pass gate FINFETs;   wherein the seventh, eighth, and ninth fins include source, channel, and drain regions of fourth, fifth, and sixth pull-down FINFETs respectively, and the eighth fin further includes source, channel, and drain regions of a third pass gate FINFET, wherein the drain region of the fifth pull-down FINFET and the source region of the third pass gate FINFET share a second common region in the eighth fin;   wherein the tenth fin includes source, channel, and drain regions of a fourth pass gate FINFET;   a first gate electrode oriented in the first direction and over the channel regions of the first pull-up FINFET and the first, second, and third pull-down FINFETs;   a second gate electrode oriented in the first direction and over the channel regions of the second pull-up FINFET, and the fourth, fifth, and sixth pull-down FINFETs;   a first contact feature that electrically connects to at least the drain region of the first pull-up FINFET, the drain regions of the first, second, and third pull-down FINFETs, the source region of the first pass gate FINFET, and the second gate electrode; and   a second contact feature that electrically connects to at least the drain region of the second pull-up FINFET, the drain regions of the fourth, fifth, and sixth pull-down FINFETs, the source region of the third pass gate FINFET, and the first gate electrode; and   a read port that includes at least two pull-down FINFETs in parallel and at least two pass gate FINFETs in parallel.   
     
     
       45. The SRAM cell of claim 44, further comprising:
 a third gate electrode oriented in the first direction and over the channel regions of the first and second pass gate FINFETs; and   a fourth gate electrode oriented in the first direction and over the channel regions of the third and fourth pass gate FINFETs.   
     
     
       46. The SRAM cell of claim 45, further comprising:
 a third contact feature that electrically connects the source region of the first pull-up FINFET to a first power line;   a fourth contact feature that electrically connects the source regions of the first, second, and third pull-down FINFETs to a second power line;   a fifth contact feature that electrically connects the drain region of the first pass gate FINFET to a first bit line;   a sixth contact feature that electrically connects the drain region of the second pass gate FINFET to a second bit line;   a seventh contact feature that electrically connects the third gate electrode to a first word line;   a eighth contact feature that electrically connects the source region of the second pull-up FINFET to the first power line;   a ninth contact feature that electrically connects the source regions of the fourth, fifth, and sixth pull-down FINFETs to the second power line;   a tenth contact feature that electrically connects the drain region of the third pass gate FINFET to a third bit line;   a eleventh contact feature that electrically connects the drain region of the fourth pass gate FINFET to a fourth bit line; and   a twelfth contact feature that electrically connects the fourth gate electrode to a second word line.   
     
     
       47. The SRAM cell of claim 44, wherein the first and second contact features and the first and second gate electrodes are in a same interconnect level of the SRAM cell. 
     
     
       48. The SRAM cell of claim 44, wherein each of the first and second contact features has a general L-shape with a first portion of the L-shape oriented generally in the first direction and a second portion of the L-shape oriented generally in the second direction. 
     
     
       49. The SRAM cell of claim 44, further comprising:
 a first conductive feature that electrically connects to the source region of the second pass gate FINFET and the first gate electrode; and   a second conductive feature that electrically connects to the source region of the fourth pass gate FINFET and the second gate electrode, wherein the first and second conductive features and the first and second gate electrodes are in a same interconnect level of the SRAM cell.   
     
     
       50. The SRAM cell of claim 44, wherein the first gate electrode lands on the source region of the second pass gate FINFET, and the second gate electrode lands on the source region of the fourth pass gate FINFET.