Memory cell

Abstract

A memory cell and array and a method of forming a memory cell and array are described. A memory cell includes first and second pull-up transistors, first and second pull-down transistors, first and second pass-gate transistors, and first and second isolation transistors. Drains of the first pull-up and first pull-down transistors are electrically coupled together at a first node. Drains of the second pull-up and second pull-down transistors are electrically coupled together at a second node. Gates of the second pull-up and second pull-down transistors are electrically coupled to the first node, and gates of the first pull-up and first pull-down transistors are electrically coupled to the second node. The first and second pass-gate transistors are electrically coupled to the first and second nodes, respectively. The first and second isolation transistors are electrically coupled to the first and second nodes, respectively.

What is claimed is: 
     
       1. A memory array comprising:
 a first active area, a second active area, a third active area, and a fourth active area each traversing a first memory cell area and a second memory cell area, the first memory cell area being adjacent to the second memory cell area; 
 wherein in the first memory cell area:
 the first active area is a component of a first pull-down transistor, 
 the second active area is a component of a first pull-up transistor, a drain of the first pull-up transistor being electrically coupled to a drain of the first pull-down transistor at a first node, 
 the third active area is a component of a first isolation transistor and a second pull-up transistor, and 
 the fourth active area is a component of a second pull-down transistor, a drain of the second pull-up transistor being electrically coupled to a drain of the second pull-down transistor at a second node, a gate of the second pull-up transistor and a gate of the second pull-down transistor being electrically coupled to the first node, a gate of the first pull-up transistor and a gate of the first pull-down transistor being electrically coupled to the second node; 
 
 wherein in the second memory cell area:
 the first active area is a component of a third pull-down transistor, 
 the second active area is a component of a third pull-up transistor, a drain of the third pull-up transistor being electrically coupled to a drain of the third pull-down transistor at a third node, 
 the third active area is a component of a second isolation transistor and a fourth pull-up transistor, and 
 the fourth active area is a component of a fourth pull-down transistor, a drain of the fourth pull-up transistor being electrically coupled to a drain of the fourth pull-down transistor at a fourth node, a gate of the fourth pull-up transistor and a gate of the fourth pull-down transistor being electrically coupled to the third node, a gate of the third pull-up transistor and a gate of the third pull-down transistor being electrically coupled to the fourth node; and 
 
 wherein the first isolation transistor and the second isolation transistor have a shared source/drain region at a boundary between the first memory cell area and the second memory cell area, the shared source/drain region not having a contact directly coupled thereto. 
 
     
     
       2. The memory array of  claim 1 , wherein:
 in the first memory cell area:
 the first active area is a component of a first pass-gate transistor, and 
 the fourth active area is a component of a second pass-gate transistor, and in the second memory cell area: 
 the first active area is a component of a third pass-gate transistor, and 
 the fourth active area is a component of a fourth pass-gate transistor. 
 
 
     
     
       3. The memory array of  claim 1  further comprising a fifth active area and a sixth active area each traversing the first memory cell area and the second memory cell area,
 wherein in the first memory cell area:
 the fifth active area is a further component of the first pull-down transistor, and 
 the sixth active area is a further component of the second pull-down transistor, and 
 
 wherein in the second memory cell area:
 the fifth active area is a further component of the third pull-down transistor, and 
 the sixth active area is a further component of the fourth pull-down transistor. 
 
 
     
     
       4. The memory array of  claim 1 , wherein each of the first active area, the second active area, the third active area, and the fourth active area comprises a fin active area. 
     
     
       5. The memory array of  claim 1  further comprising a first metallization layer over the active areas and a second metallization layer over the first metallization layer, one of the first metallization layer or the second metallization layer comprising a bit line trace traversing the first memory cell area and the second memory cell area, the other of the first metallization layer or the second metallization layer comprising a first word line trace extending across the first memory cell area at a direction that intersects the bit line trace and a second word line trace extending across the second memory cell area at a direction that intersects the bit line trace. 
     
     
       6. The memory array of  claim 5 , wherein the one of the first metallization layer or the second metallization layer further comprises a power trace traversing the first memory cell area and the second memory cell area, and the other of the first metallization layer or the second metallization layer further comprises a first ground trace extending across the first memory cell area at a direction that intersects the bit line trace and a second ground trace extending across the second memory cell area at a direction that intersects the bit line trace. 
     
     
       7. The memory array of  claim 5 , wherein the one of the first metallization layer or the second metallization layer further comprises a power trace traversing the first memory cell area and the second memory cell area, and further comprises a ground trace traversing the first memory cell area and the second memory cell area. 
     
     
       8. The memory array of  claim 5 , wherein the one of the first metallization layer or the second metallization layer further comprises (i) a power trace traversing the first memory cell area and the second memory cell area, (ii) a first ground trace traversing the first memory cell area and the second memory cell area, and (iii) a second ground trace traversing the first memory cell area and the second memory cell area, and the other of the first metallization layer or the second metallization layer further comprises a ground mesh trace, a first via electrically coupling the ground mesh trace to the first ground trace, and a second via electrically coupling the ground mesh trace to the second ground trace. 
     
     
       9. The memory array of  claim 1 , further comprising a fifth active area and a sixth active area each traversing the first memory cell area and the second memory cell area,
 wherein in the first memory cell area:
 the first active area is a component of a first pass-gate transistor, 
 the fourth active area is a component of a second pass-gate transistor, 
 the fifth active area is a component of a third pass-gate transistor, and 
 the sixth active area is a component of a fourth pass-gate transistor, and 
 
 wherein in the second memory cell area:
 the first active area is a component of a fifth pass-gate transistor, 
 the fourth active area is a component of a sixth pass-gate transistor, 
 the fifth active area is a component of a seventh pass-gate transistor, and 
 the sixth active area is a component of a eighth pass-gate transistor. 
 
 
     
     
       10. The memory array of  claim 1 , further comprising a fifth active area traversing the first memory cell area and the second memory cell area,
 wherein in the first memory cell area:
 the fifth active area is a component of a first read pass-gate transistor and a first read pull-down transistor, and 
 
 wherein in the second memory cell area:
 the fifth active area is a component of a second read pass-gate transistor and a second read pull-down transistor. 
 
 
     
     
       11. A memory array comprising:
 a first static random access memory (SRAM) cell area on a substrate; and 
 a second SRAM cell area on the substrate, the first SRAM cell area adjoining the second SRAM cell area at a boundary, a fin active area being in each of the first SRAM cell area and the second SRAM cell area and extending across the boundary, the fin active area being (i) a component of a first isolation transistor in the first SRAM cell area, (ii) a component of a first operational transistor in the first SRAM cell area, (iii) a component of a second isolation transistor in the second SRAM cell area, and (iv) a component of a second operational transistor in the second SRAM cell area. 
 
     
     
       12. The memory array of  claim 11 , wherein each of the first SRAM cell area and the second SRAM cell area comprises:
 a first pull-down transistor, 
 a first pull-up transistor, a drain of the first pull-up transistor being electrically coupled to a drain of the first pull-down transistor at a first node, the first pull-up transistor in the first SRAM cell area being the first operational transistor, and the first pull-up transistor in the second SRAM cell area being the second operational transistor, 
 a second pull-up transistor, and 
 a second pull-down transistor, a drain of the second pull-up transistor being electrically coupled to a drain of the second pull-down transistor at a second node, a gate of the second pull-up transistor and a gate of the second pull-down transistor being electrically coupled to the first node, a gate of the first pull-up transistor and a gate of the first pull-down transistor being electrically coupled to the second node. 
 
     
     
       13. The memory array of  claim 11 , wherein each of the first SRAM cell area and the second SRAM cell area comprises a double pitch transistor. 
     
     
       14. The memory array of  claim 11 , wherein each of the first SRAM cell area and the second SRAM cell area comprises a dual port SRAM cell. 
     
     
       15. The memory array of  claim 11 , wherein each of the first SRAM cell area and the second SRAM cell area comprises a two-port SRAM cell. 
     
     
       16. A method comprising:
 forming a fin active area on a substrate, the fin active area extending across a boundary of a first static random access memory (SRAM) cell area into a second SRAM cell area; 
 forming a first gate structure over the fin active area in the first SRAM cell area proximate the boundary and a second gate structure over the fin active area in the second SRAM cell area proximate the boundary; 
 forming a dielectric layer over the fin active area, the first gate structure, and the second gate structure; and 
 forming a first contact through the dielectric layer to a source/drain region of the fin active area in the first SRAM cell area and a second contact through the dielectric layer to a source/drain region of the fin active area in the second SRAM cell area, the first contact being on an opposite side of the first gate structure from the boundary, the second contact being on an opposite side of the second gate structure from the boundary, no contact being formed to a region of the fin active area at the boundary between the first gate structure and the second gate structure. 
 
     
     
       17. The method of  claim 16  further comprising:
 forming a first metallization layer over the substrate; and 
 forming a second metallization layer over the first metallization layer, one of the first metallization layer or the second metallization layer comprising a bit line trace traversing the first SRAM cell area and the second SRAM cell area, the other of the first metallization layer or the second metallization layer comprising a first word line trace extending across the first SRAM cell area at a direction that intersects the bit line trace and a second word line trace extending across the second SRAM cell area at a direction that intersects the bit line trace. 
 
     
     
       18. The method of  claim 17 , wherein the one of the first metallization layer or the second metallization layer further comprises a power trace traversing the first SRAM cell area and the second SRAM cell area, and the other of the first metallization layer or the second metallization layer further comprises a first ground trace extending across the first SRAM cell area at a direction that intersects the bit line trace and a second ground trace extending across the second SRAM cell area at a direction that intersects the bit line trace. 
     
     
       19. The method of  claim 17 , wherein the one of the first metallization layer or the second metallization layer further comprises a power trace traversing the first SRAM cell area and the second SRAM cell area, and further comprises a ground trace traversing the first SRAM cell area and the second SRAM cell area. 
     
     
       20. The method of  claim 17 , wherein the one of the first metallization layer or the second metallization layer further comprises (i) a power trace traversing the first SRAM cell area and the second SRAM cell area, (ii) a first ground trace traversing the first SRAM cell area and the second SRAM cell area, and (iii) a second ground trace traversing the first SRAM cell area and the second SRAM cell area, and the other of the first metallization layer or the second metallization layer further comprises a ground mesh trace, a first via electrically coupling the ground mesh trace to the first ground trace, and a second via electrically coupling the ground mesh trace to the second ground trace. 
     
     
       21. A memory array comprising:
 a first active area, a second active area, a third active area, and a fourth active area each traversing a first memory cell area and a second memory cell area, the first memory cell area being adjacent to the second memory cell area;   wherein in the first memory cell area:
 the first active area is a component of a first pull-down transistor, 
 the second active area is a component of a first pull-up transistor, a drain of the first pull-up transistor being electrically coupled to a drain of the first pull-down transistor at a first node, 
 the third active area is a component of a first isolation transistor and a second pull-up transistor, and 
 the fourth active area is a component of a second pull-down transistor, a drain of the second pull-up transistor being electrically coupled to a drain of the second pull-down transistor at a second node, a gate of the second pull-up transistor and a gate of the second pull-down transistor being electrically coupled to the first node, a gate of the first pull-up transistor and a gate of the first pull-down transistor being electrically coupled to the second node; 
   wherein in the second memory cell area:
 the first active area is a component of a third pull-down transistor, 
 the second active area is a component of a third pull-up transistor, a drain of the third pull-up transistor being electrically coupled to a drain of the third pull-down transistor at a third node, 
 the third active area is a component of a second isolation transistor and a fourth pull-up transistor, and 
 the fourth active area is a component of a fourth pull-down transistor, a drain of the fourth pull-up transistor being electrically coupled to a drain of the fourth pull-down transistor at a fourth node, a gate of the fourth pull-up transistor and a gate of the fourth pull-down transistor being electrically coupled to the third node, a gate of the third pull-up transistor and a gate of the third pull-down transistor being electrically coupled to the fourth node; and 
   wherein the first isolation transistor and the second isolation transistor have a shared source/drain region at a boundary between the first memory cell area and the second memory cell area.   
     
     
       22. The memory array of claim 21, wherein:
 in the first memory cell area:
 the first active area is a component of a first pass-gate transistor, and 
 the fourth active area is a component of a second pass-gate transistor, and 
   in the second memory cell area:
 the first active area is a component of a third pass-gate transistor, and 
 the fourth active area is a component of a fourth pass-gate transistor. 
   
     
     
       23. The memory array of claim 21 further comprising a fifth active area and a sixth active area each traversing the first memory cell area and the second memory cell area,
 wherein in the first memory cell area:
 the fifth active area is a further component of the first pull-down transistor, and 
 the sixth active area is a further component of the second pull-down transistor, and 
   wherein in the second memory cell area:
 the fifth active area is a further component of the third pull-down transistor, and 
 the sixth active area is a further component of the fourth pull-down transistor. 
   
     
     
       24. The memory array of claim 21, wherein each of the first active area, the second active area, the third active area, and the fourth active area comprises a fin active area. 
     
     
       25. The memory array of claim 21 further comprising a first metallization layer over the active areas and a second metallization layer over the first metallization layer, one of the first metallization layer or the second metallization layer comprising a bit line trace traversing the first memory cell area and the second memory cell area, the other of the first metallization layer or the second metallization layer comprising a first word line trace extending across the first memory cell area at a direction that intersects the bit line trace and a second word line trace extending across the second memory cell area at a direction that intersects the bit line trace. 
     
     
       26. The memory array of claim 25, wherein the one of the first metallization layer or the second metallization layer further comprises a power trace traversing the first memory cell area and the second memory cell area, and the other of the first metallization layer or the second metallization layer further comprises a first ground trace extending across the first memory cell area at a direction that intersects the bit line trace and a second ground trace extending across the second memory cell area at a direction that intersects the bit line trace. 
     
     
       27. The memory array of claim 25, wherein the one of the first metallization layer or the second metallization layer further comprises a power trace traversing the first memory cell area and the second memory cell area, and further comprises a ground trace traversing the first memory cell area and the second memory cell area. 
     
     
       28. The memory array of claim 25, wherein the one of the first metallization layer or the second metallization layer further comprises (i) a power trace traversing the first memory cell area and the second memory cell area, (ii) a first ground trace traversing the first memory cell area and the second memory cell area, and (iii) a second ground trace traversing the first memory cell area and the second memory cell area, and the other of the first metallization layer or the second metallization layer further comprises a ground mesh trace, a first via electrically coupling the ground mesh trace to the first ground trace, and a second via electrically coupling the ground mesh trace to the second ground trace. 
     
     
       29. The memory array of claim 21, further comprising a fifth active area and a sixth active area each traversing the first memory cell area and the second memory cell area,
 wherein in the first memory cell area:
 the first active area is a component of a first pass-gate transistor, 
 the fourth active area is a component of a second pass-gate transistor, 
 the fifth active area is a component of a third pass-gate transistor, and 
 the sixth active area is a component of a fourth pass-gate transistor, and 
   wherein in the second memory cell area:
 the first active area is a component of a fifth pass-gate transistor, 
 the fourth active area is a component of a sixth pass-gate transistor, 
 the fifth active area is a component of a seventh pass-gate transistor, and 
 the sixth active area is a component of a eighth pass-gate transistor. 
   
     
     
       30. The memory array of claim 21, further comprising a fifth active area traversing the first memory cell area and the second memory cell area,
 wherein in the first memory cell area:
 the fifth active area is a component of a first read pass-gate transistor and a first read pull-down transistor, and 
   wherein in the second memory cell area:
 the fifth active area is a component of a second read pass-gate transistor and a second read pull-down transistor. 
   
     
     
       31. A memory cell comprising:
 a first pull-up transistor and a first pull-down transistor, a drain of the first pull-up transistor being electrically coupled to a drain of the first pull-down transistor at a first node;   a second pull-up transistor and a second pull-down transistor, a drain of the second pull-up transistor being electrically coupled to a drain of the second pull-down transistor at a second node, a gate of the second pull-up transistor and a gate of the second pull-down transistor being electrically coupled to the first node, a gate of the first pull-up transistor and a gate of the first pull-down transistor being electrically coupled to the second node;   a first pass-gate transistor electrically coupled to the first node;   a second pass-gate transistor electrically coupled to the second node;   a first isolation transistor electrically coupled to the first node; and   a second isolation transistor electrically coupled to the second node, wherein the first isolation transistor is configured to have a source and a gate coupled to the first node, and the second isolation transistor is configured to have a source and a gate coupled to the second node.   
     
     
       32. The memory cell of claim 31, wherein a drain of the first isolation transistor is floating. 
     
     
       33. The memory cell of claim 32, wherein a bit line (BL) or power voltage (VDD) is formed over the drain of the first isolation transistor. 
     
     
       34. The memory cell of claim 32, wherein the drain of the first isolation transistor is sandwiched between a bit line (BL) and a power voltage (VDD). 
     
     
       35. The memory cell of claim 31, wherein a drain of the second isolation transistor is floating. 
     
     
       36. The memory cell of claim 35, wherein a complementary bit line (BLB) or a power voltage (VDD) is formed over the drain of the second isolation transistor. 
     
     
       37. The memory cell of claim 35, wherein the drain of the second isolation transistor is sandwiched between a complementary bit line (BLB) and a power voltage (VDD). 
     
     
       38. The memory cell of claim 31, wherein a word line (WL) is formed over the first and second isolation transistors. 
     
     
       39. The memory cell of claim 31, wherein a drain of the first isolation transistor is formed at a first side of a word line (WL), a drain of the second isolation transistor is formed at a second side of the WL. 
     
     
       40. The memory cell of claim 31, wherein a first word line (AWL) or a second word line (BWL) is formed over a drain of the first isolation transistor. 
     
     
       41. The memory cell of claim 31, wherein a first word line (AWL) or a second word line (BWL) is formed over a drain of the second isolation transistor. 
     
     
       42. The memory cell of claim 31, wherein a write word line (WWL) or a read word line (RWL) is formed over a drain of the first isolation transistor. 
     
     
       43. The memory cell of claim 31, wherein a write word line (WWL) or a read word line (RWL) is formed over a drain of the second isolation transistor.