Non-volatile semiconductor storage device

Abstract

Memory strings includes: a first semiconductor layer including a columnar portion extending in a direction perpendicular to a substrate; a first electric charge storage layer formed to surround a side surface of the columnar portion; and a first conductive layer formed to surround the first electric charge storage layer. First selection transistors includes: a second semiconductor layer extending upward from a top surface of the columnar portion; a second electric charge storage layer formed to surround a side surface of the second semiconductor layer; and a second conductive layer formed to surround the second electric charge storage layer. The non-volatile semiconductor storage device further includes a control circuit that causes, prior to reading data from a selected one of the memory strings, electric charges to be accumulated in the second electric charge storage layer of one of the first selection transistors connected to an unselected one of the memory strings.

What is claimed is: 
     
       1. A non-volatile semiconductor storage device comprising:
 a plurality of memory strings, each having a plurality of electrically rewritable memory cells connected in series; and   a plurality of first selection transistors connected to one ends of the respective memory strings,   each of the memory strings comprising:
 a first semiconductor layer including a columnar portion extending in a direction perpendicular to a substrate; 
 a first electric charge storage layer formed to surround a side surface of the columnar portion; and 
 a first conductive layer formed to surround a side surface of the columnar portion as well as the first electric charge storage layer, the first conductive layer functioning as a control electrode of a respective one of the memory cells, 
   each of the first selection transistors comprising:
 a second semiconductor layer extending upward from a top surface of the columnar portion; 
 a second electric charge storage layer formed to surround a side surface of the second semiconductor layer; and 
 a second conductive layer formed to surround a side surface of the second semiconductor layer as well as the second electric charge storage layer, the second conductive layer functioning as a control electrode of a respective one of the first selection transistors, 
   the non-volatile semiconductor storage device further comprising a control circuit configured to cause, prior to reading data from a selected one of the memory strings, electric charges to be accumulated in the second electric charge storage layer of one of the first selection transistors connected to an unselected one of the memory strings.   
     
     
       2. The non-volatile semiconductor storage device according to  claim 1 , wherein
 a plurality of memory blocks each includes a plurality of the memory strings arranged in a matrix form, and   prior to reading data from a selected one of the memory strings in a selected one of the memory blocks, the control circuit causes electric charges to be accumulated in the second electric charge storage layer of one of the first selection transistors connected to an unselected one of the memory strings in the selected memory block.   
     
     
       3. The non-volatile semiconductor storage device according to  claim 1 , wherein
 a plurality of memory blocks each includes a plurality of the memory strings arranged in a matrix form, and   prior to reading data from a selected one of the memory strings in a selected one of the memory blocks, the control circuit causes electric charges to be accumulated in the second electric charge storage layers of the first selection transistors connected to the memory strings in an unselected one of the memory blocks.   
     
     
       4. The non-volatile semiconductor storage device according to  claim 1 , wherein
 a plurality of memory blocks each includes a plurality of the memory strings arranged in a matrix form, and   prior to reading data from a selected one of the memory strings in a selected one of the memory blocks, the control circuit causes electric charges to be accumulated in the second electric charge storage layer of one of the first selection transistors connected to an unselected one of the memory strings in the selected memory block, and also causes electric charges to be accumulated in the second electric charge storage layers of the first selection transistors connected to the memory strings in an unselected one of the memory blocks.   
     
     
       5. The non-volatile semiconductor storage device according to  claim 1 , wherein
 after reading data from a selected one of the memory strings, the control circuit causes electric charges to be discharged from the second electric charge storage layer of one of the first selection transistors connected to an unselected one of the memory strings.   
     
     
       6. The non-volatile semiconductor storage device according to  claim 5 , wherein
 the control circuit is configured to generate a GIDL current near a gate of one of the first selection transistors connected to an unselected one of the memory strings to boost a voltage at the second semiconductor layer to a first voltage by the GIDL current,   thereby discharging electric charges stored in the second electric charge storage layer.   
     
     
       7. The non-volatile semiconductor storage device according to  claim 1 , wherein
 the control circuit causes electric charges to be accumulated in the second electric charge storage layer by boosting in a step-like manner to be applied to a gate of one of the first selection transistors connected to an unselected one of the memory strings.   
     
     
       8. The non-volatile semiconductor storage device according to  claim 1 , comprising:
 a plurality of second selection transistors connected to the other ends of the memory strings,   wherein each of the second selection transistors comprises:
 a third semiconductor layer extending downward from a bottom surface of the first semiconductor layer; 
 a third electric charge storage layer formed to surround a side surface of the third semiconductor layer; and 
 a third conductive layer formed to surround a side surface of the third semiconductor layer as well as the third electric charge storage layer, the third conductive layer functioning as a control electrode of a respective one of the second selection transistors, and 
   prior to reading data from a selected one of the memory strings, the control circuit causes electric charges to be accumulated in the third electric charge storage layer of one of the second selection transistors connected to an unselected one of the memory strings.   
     
     
       9. The non-volatile semiconductor storage device according to  claim 8 , wherein
 a plurality of memory blocks each includes a plurality of the memory strings arranged in a matrix form, and   prior to reading data from a selected one of the memory strings in a selected one of the memory blocks, the control circuit causes electric charges to be accumulated in the third electric charge storage layer of one of the second selection transistors connected to an unselected one of the memory strings in the selected memory block.   
     
     
       10. The non-volatile semiconductor storage device according to  claim 8 , wherein
 a plurality of memory blocks each includes a plurality of the memory strings arranged in a matrix form, and   prior to reading data from a selected one of the memory strings in a selected one of the memory blocks, the control circuit causes electric charges to be accumulated in the third electric charge storage layers of the second selection transistors connected to the memory strings in an unselected one of the memory blocks.   
     
     
       11. The non-volatile semiconductor storage device according to  claim 8 , wherein
 a plurality of memory blocks each includes a plurality of the memory strings arranged in a matrix form, and   prior to reading data from a selected one of the memory strings in a selected one of the memory blocks, the control circuit causes electric charges to be accumulated in the third electric charge storage layer of one of the second selection transistors connected to an unselected one of the memory strings in the selected memory block, and also causes electric charges to be accumulated in the third electric charge storage layers of the second selection transistors connected to the memory strings in an unselected one of the memory blocks.   
     
     
       12. The non-volatile semiconductor storage device according to  claim 8 , wherein
 after reading data from a selected one of the memory strings, the control circuit causes electric charges to be discharged from the third electric charge storage layer of one of the second selection transistors connected to an unselected one of the memory strings.   
     
     
       13. The non-volatile semiconductor storage device according to  claim 12 , wherein
 the control circuit is configured to generate a GIDL current near a gate of one of the second selection transistors connected to an unselected one of the memory strings to boost a voltage at the third semiconductor layer to a second voltage by the GIDL current,   thereby discharging electric charges stored in the third electric charge storage layer.   
     
     
       14. The non-volatile semiconductor storage device according to  claim 8 , wherein
 the control circuit causes electric charges to be accumulated in the third electric charge storage layer by boosting in a step-like manner a voltage to be applied to a gate of one of the second selection transistors connected to an unselected one of the memory strings.   
     
     
       15. The non-volatile semiconductor storage device according to  claim 1 , wherein
 the first semiconductor layer comprises a joining portion formed to join bottom ends of a pair of the columnar portions.   
     
     
       16. A non-volatile semiconductor storage device comprising:
 a plurality of memory strings, each having a plurality of electrically rewritable memory cells connected in series; and   a plurality of first selection transistors connected to one ends of the respective memory strings,   each of the memory strings comprising:
 a first semiconductor layer including a columnar portion extending in a direction perpendicular to a substrate; 
 a first electric charge storage layer formed to surround a side surface of the columnar portion; and 
 a first conductive layer formed to surround a side surface of the columnar portion as well as the first electric charge storage layer, the first conductive layer functioning as a control electrode of a respective one of the memory cells, 
   each of the first selection transistors comprising:
 a second semiconductor layer extending downward from a bottom surface of the columnar portion; 
 a second electric charge storage layer formed to surround a side surface of the second semiconductor layer; and 
 a second conductive layer formed to surround a side surface of the second semiconductor layer as well as the second electric charge storage layer, the second conductive layer functioning as a control electrode of a respective one of the first selection transistors, 
   the non-volatile semiconductor storage device further comprising a control circuit configured to cause, prior to reading data from a selected one of the memory strings, electric charges to be accumulated in the second electric charge storage layer of one of the first selection transistors connected to an unselected one of the memory strings.   
     
     
       17. The non-volatile semiconductor storage device according to  claim 16 , wherein
 a plurality of memory blocks each includes a plurality of the memory strings arranged in a matrix form, and   prior to reading data from a selected one of the memory strings in a selected one of the memory blocks, the control circuit causes electric charges to be accumulated in the second electric charge storage layer of one of the first selection transistors connected to an unselected one of the memory strings in the selected memory block.   
     
     
       18. The non-volatile semiconductor storage device according to  claim 16 , wherein
 a plurality of memory blocks each includes a plurality of the memory strings arranged in a matrix form, and   prior to reading data from a selected one of the memory strings in a selected one of the memory blocks, the control circuit causes electric charges to be accumulated in the second electric charge storage layers of the first selection transistors connected to the memory strings in an unselected one of the memory blocks.   
     
     
       19. The non-volatile semiconductor storage device according to  claim 16 , wherein
 a plurality of memory blocks each includes a plurality of the memory strings arranged in a matrix form, and   prior to reading data from a selected one of the memory strings in a selected one of the memory blocks, the control circuit causes electric charges to be accumulated in the second electric charge storage layer of one of the first selection transistors connected to an unselected one of the memory strings in the selected memory block, and also causes electric charges to be accumulated in the second electric charge storage layers of the first selection transistors connected to the memory strings in an unselected one of the memory blocks.   
     
     
       20. The non-volatile semiconductor storage device according to  claim 16 , wherein
 after reading data from a selected one of the memory strings, the control circuit causes electric charges to be discharged from the second electric charge storage layer of one of the first selection transistors connected to an unselected one of the memory strings.   
     
     
       21. A non-volatile semiconductor storage device comprising:
 a plurality of memory strings including a plurality of memory cells, the memory strings including a first memory string and a second memory string,   a first selection transistor coupled to one end of the first memory string and a bit line;   a second selection transistor coupled to one end of the second memory string and the bit line;   a word line coupled to a gate of one of the memory cells in the first memory string and a gate of one of the memory cells in the second memory string;   a first line coupled to a gate of the first selection transistor;   a second line coupled to a gate of the second selection transistor; and   a controller configured to perform a pre-program operation and a program operation, the pre-program operation including a first phase and the program operation including a second phase,   the controller configured to apply a first program voltage to the first line, a first voltage to the second line, and a second voltage to the word line during the first phase, and the controller configured to apply a third voltage to the first line, a fourth voltage to the second line, and a second program voltage to the word line during the second phase;   wherein the first program voltage and the second program voltage are higher than the first voltage, the second voltage, the third voltage, and the fourth voltage.    
     
     
       22. The non-volatile semiconductor storage device according to claim 21 wherein the controller is configured to program one of the memory cells in the program operation.  
     
     
       23. The non-volatile semiconductor storage device according to claim 21 wherein the first, second, and fourth voltages are zero voltages and the first program voltage is substantially same as the second program voltage.  
     
     
       24. The non-volatile semiconductor storage device according to claim 21 wherein the program operation includes a third phase before the second phase;
 the controller further configured to apply a fifth voltage to the first line and apply a sixth voltage to the word line, the fifth voltage being substantially same as the sixth voltage, in the third phase.    
     
     
       25. The non-volatile semiconductor storage device according to claim 24 wherein the fifth voltage is higher than zero voltage and lower than the first program voltage and the second program voltage.  
     
     
       26. The non-volatile semiconductor storage device according to claim 21 wherein the controller is configured to perform a pre-program erase operation including a fourth phase;
 the controller further configured to apply a seventh voltage to the first line and set the word line in a floating state during the fourth phase, wherein the seventh voltage is lower than the first program voltage and the second program voltage and the seventh voltage is higher than the first voltage, the second voltage, the third voltage, and the fourth voltage.    
     
     
       27. The non-volatile semiconductor storage device according to claim 26 wherein the controller is configured to perform the pre-program operation, a read operation, and the pre-program erase operation in this order.  
     
     
       28. A non-volatile semiconductor storage device comprising:
 a plurality of memory strings including a plurality of memory cells, the memory strings including a first memory string and a second memory string,   a first selection transistor coupled to one end of the first memory string and a source line;   a second selection transistor coupled to one end of the second memory string and the source line;   a word line electrically coupled to a gate of one of the memory cells in the first memory string and a gate of one of the memory cells in the second memory string;   a first line coupled to a gate of the first selection transistor;   a second line coupled to a gate of the second selection transistor; and   a controller configured to perform a pre-program operation and a program operation, the pre-program operation including a first phase and the program operation including a second phase,   the controller configured to apply a first program voltage to the first line, a first voltage to the second line, and a second voltage to the word line during the first phase, and   the controller configured to apply a third voltage to the first line and a fourth voltage to the second line and a second program voltage to the word line during the second phase,   wherein the first program voltage and the second program voltage are higher than the first voltage, the second voltage, the third voltage, and the fourth voltage.    
     
     
       29. The non-volatile semiconductor storage device according to claim 28 wherein the first, second, and fourth voltages are zero voltages and the first program voltage is substantially same as the second program voltage.  
     
     
       30. The non-volatile semiconductor storage device according to claim 28 wherein the program operation includes a third phase;
 the controller further configured to apply a fifth voltage to the first line and apply a sixth voltage to the word line, the fifth voltage being higher than the sixth voltage, and the fifth voltage being higher than the third voltage, in the third phase after the second phase.    
     
     
       31. The non-volatile semiconductor storage device according to claim 30 wherein the fifth voltage is higher than zero voltage and lower than the first program voltage and the second program voltage.  
     
     
       32. The non-volatile semiconductor storage device according to claim 28 wherein the controller is further configured to perform the pre-program operation before a read operation.  
     
     
       33. The non-volatile semiconductor storage device according to claim 32 wherein the controller is further configured to perform a pre-program erase operation including a fourth phase; the controller further configured to apply a seventh voltage to the first line and set the word line in a floating stat during the fourth phase, wherein the seventh voltage is lower than the first program voltage and the second program voltage and the seventh voltage are higher than the first to fourth voltages.  
     
     
       34. The non-volatile semiconductor storage device according to claim 33 wherein the controller is configured to perform the pre-program operation, a read operation, and the pre-program erase operation in this order.