Data security method and device for computer modules

Abstract

A security method for an attached computer module in a computer system. The security method reads a security identification number in an attached computer module and compares it to a security identification number in a console, which houses the attached computer module. Based upon a relationship between these numbers, a security status is selected. The security status determines the security level of operating the computer system.

What is claimed is: 
     
       1. A security protection method for a computer module, said method comprising:
 inserting the computer module into a console;   initiating a security program in said module to read a security identification of said console and to read a security identification of said computer module;   determining of a predetermined security status based upon a relationship of said console identification and said computer module identification;   selecting said predetermined security status; and   operating said computer module based upon said security status.   
     
     
       2. The method of  claim 1  wherein said predetermined security status disables a network access to the computer module. 
     
     
       3. The method of  claim 1  wherein said predetermined security status disables a secondary storage of information from said computer module to substantially prevent information to be transferred from a memory of the computer module to said secondary storage. 
     
     
       4. The method of  claim 1  wherein said security program is provided in a system BIOS. 
     
     
       5. The method of  claim 1  wherein said step of initiating reads said security identification of said computer module from a flash memory device. 
     
     
       6. The method of  claim 1  wherein said step of initiating reads said security identification of said console from a flash memory device. 
     
     
       7. The method of  claim 1  wherein said console is selected from a desktop home computing device, an office desktop computing device, a mobile computing device, a television sot-top computing device, and a co-worker's computing device. 
     
     
       8. A system for secured information transactions, the system comprising:
 a console comprising a peripheral controller housed in the console;   a user identification input device coupled to the peripheral controller, the user identification input device being provided for user identification data; and   an attached computer module coupled to the console, the attached computer module comprising a security memory device stored with the user identification data.   
     
     
       9. The system of  claim 8  wherein the user identification input device is a finger print reader. 
     
     
       10. The system of  claim 8  wherein the user identification input device is a voice processing device. 
     
     
       11. A method for operating a module computer into one of a plurality of network systems, the method comprising:
 providing a computer module, the module comprising a connection program;   inserting the computer module into a computer console, the computer console having access to a network;   receiving connection information from the computer console;   configuring the connection program to adapt to the connection information; and   establish a connection between the computer module and a server coupled to the network.   
     
     
       12. The method of  claim 11  wherein the connection information comprises a connection protocol for providing the connection. 
     
     
       13. The method of  claim 12  wherein the connection protocol is selected from TCP/IP, or mobile IP. 
     
     
       14. A computer system, comprising:
 a central processing unit (CPU);   a low voltage differential signal (LVDS) channel directly extending from the CPU, the LVDS channel comprising two unidirectional, serial bit channels to convey data in opposite directions; and   a mass storage device directly coupled to the CPU;   wherein the CPU is configured to output a serial bit stream of Universal Serial Bus (USB) protocol information that is conveyed over the LVDS channel.    
     
     
       15. The computer system of claim 14 wherein the mass storage device comprises flash memory.  
     
     
       16. The computer system of claim 14 further comprising a second LVDS channel extending directly from the CPU, comprising two unidirectional, serial bit channels to convey data in opposite directions.  
     
     
       17. The computer system of claim 16 wherein the serial bit channels conveys address and data bits of a Peripheral Component Interface (PCI) bus transaction.  
     
     
       18. The computer system of claim 17 wherein the second LVDS channel couples to the mass storage device.  
     
     
       19. A computer system, comprising:
 a central processing unit (CPU);   a mass storage device directly coupled to the CPU; and   a low voltage differential signal (LVDS) channel directly extending from the CPU, the LVDS channel comprising two unidirectional, serial bit channels to convey data in opposite directions;   wherein the LVDS channel is configured to output a serial bit stream of address bits, data bits, and byte enable information bits of a Peripheral Component Interface (PCI) bus transaction.    
     
     
       20. The computer system of claim 19, wherein the mass storage device comprises flash memory.  
     
     
       21. The computer system of claim 19, wherein the LVDS channel couples to the mass storage device.  
     
     
       22. The computer system of claim 19 wherein the CPU comprises an interface controller coupled to Phase-Locked Loop (PLL) clock circuitry, and wherein the interface controller is directly coupled to the LVDS channel to convey the serial bit stream of address and data bits of the PCI bus transaction.  
     
     
       23. The computer system of claim 22 wherein the interface controller generates different data transfer rates to convey serial bit streams of address and data bits of PCI bus transactions through the LVDS channel based on different clock frequencies generated by the PLL clock circuitry.  
     
     
       24. The computer system of claim 19 wherein the central processing unit (CPU) comprises an interface controller coupled to Phase-Locked Loop (PLL) clock circuitry, and wherein the interface controller is directly coupled to the LVDS channel to convey said PCI bus transaction.  
     
     
       25. The computer system of claim 24 wherein the interface controller generates different data transfer rates to convey the PCI bus transaction through the LVDS channel based on different clock frequencies generated by the PLL clock circuitry.  
     
     
       26. A computer system, comprising:
 an integrated central processing unit and graphics subsystem in a single chip directly connected to a Low Voltage Differential Signal (LVDS) channel to convey encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in serial form, wherein the LVDS channel comprises a first unidirectional, differential signal pair to convey data in a first direction and a second unidirectional, differential signal pair to convey data in a second, opposite direction; and   a mass storage device directly coupled to the integrated central processing unit and graphics subsystem, comprising flash memory;   wherein the integrated central processing unit and graphics subsystem directly outputs a differential signal channel to convey digital video display signals.    
     
     
       27. The computer system of claim 26 wherein the differential signal channel conveys Transition Minimized Differential Signaling (TMDS) signals.  
     
     
       28. The computer system of claim 26 wherein the LVDS channel couples to the mass storage device.  
     
     
       29. A computer system, comprising:
 a printed circuit board coupled to a connector;   a central processing unit (CPU);   a first low voltage differential signal (LVDS) channel directly extending from the CPU, the LVDS channel comprising two sets of unidirectional, serial bit channels to convey an encoded serial bit stream of address bits, data bits, and byte enable information bits of a Peripheral Component Interconnect (PCI) bus transaction in opposite directions;   a mass storage device coupled to the CPU; and   a second LVDS channel coupled to the connector, comprising two sets of unidirectional, serial bit channels to convey serial bit data in opposite directions.    
     
     
       30. The computer system of claim 29 wherein the second LVDS channel communicates Ethernet protocol signals.  
     
     
       31. The computer system of claim 29 further comprising a graphics subsystem integrated with the CPU as a single chip, and wherein the integrated central processing unit and graphics subsystem directly outputs a differential signal channel to convey digital video display signals.  
     
     
       32. A computer system, comprising:
 an integrated central processing unit and graphics subsystem in a single chip directly outputting digital video display signals to a differential signal channel; and   a Low Voltage Differential Signal (LVDS) channel to convey Universal Serial Bus (USB) protocol signals, wherein the LVDS channel comprises a first unidirectional, differential signal pair to convey data in a first direction and a second unidirectional, differential signal pair to convey data in a second, opposite direction;   wherein the differential signal channel conveys Transition Minimized Differential Signaling (TMDS) signals.    
     
     
       33. The computer system of claim 32 further comprising a mass storage device directly coupled to the integrated central processing unit and graphics subsystem.  
     
     
       34. The computer system of claim 33, wherein the mass storage device comprises flash memory.  
     
     
       35. A computer system, comprising:
 a printed circuit board coupled to a connector;   a central processing unit;   a mass storage unit coupled to the central processing unit;   a first Low Voltage Differential Signal (LVDS) channel comprising two sets of unidirectional, serial bit channels to transmit data in opposite directions; and   a peripheral bridge directly coupled to the central processing unit without any intervening Peripheral Component Interconnect (PCI) bus, wherein the peripheral bridge directly conveys an encoded serial bit stream of address bits, data bits, and byte enable information bits of a PCI bus transaction over the first LVDS channel; and   a second LVDS channel coupled to the connector, comprising two sets of unidirectional, serial bit channels to convey serial bit data in opposite directions.    
     
     
       36. The computer system of claim 35 wherein the second LVDS channel communicates Ethernet protocol signals.  
     
     
       37. The computer system of claim 35 wherein the mass storage device comprises flash memory, directly coupled to the central processing unit through a third LVDS channel comprising two sets of unidirectional, serial bit channels to convey data in opposite directions.  
     
     
       38. The computer system of claim 35 wherein the peripheral bridge comprises an interface controller coupled to Phase-Locked Loop (PLL) clock circuitry, and wherein the interface controller is directly coupled to the first LVDS channel to convey encoded serial bit streams of address and data bits of PCI bus transactions.  
     
     
       39. The computer system of claim 38 wherein the interface controller generates different data transfer rates to convey the encoded serial bit streams of address and data bits of the PCI bus transactions through the first LVDS channel based on different clock frequencies generated by the PLL clock circuitry.  
     
     
       40. The computer system of claim 35 wherein the peripheral bridge comprises an interface controller coupled to Phase-Locked Loop (PLL) clock circuitry, and wherein the interface controller is directly coupled to the first LVDS channel to convey said PCI bus transaction.  
     
     
       41. The computer system of claim 40 wherein the interface controller generates different data transfer rates to convey the PCI bus transaction through the LVDS channel based on different clock frequencies generated by the PLL clock circuitry.  
     
     
       42. A computer, comprising:
 a central processing unit directly coupled to a first Low Voltage Differential Signal (LVDS) channel comprising at least two sets of unidirectional, serial bit channels to convey encoded address and data bits of a Peripheral Component Interconnect (PCI) bus transaction in serial bit streams in opposite directions;   a graphics subsystem directly coupled to a differential signal channel to convey digital video display signals;   a connector coupled to the central processing unit through a second Low Voltage Differential Signal (LVDS) channel comprising two unidirectional, differential signal pairs to convey serial bit data in opposite directions.    
     
     
       43. The computer of claim 42 wherein the CPU and graphics subsystem are integrated on a single chip.  
     
     
       44. The computer of claim 43 wherein the second LVDS channel conveys an encoded serial bit stream of address and data bits of a PCI bus transaction.  
     
     
       45. The computer of claim 42 wherein the second LVDS channel conveys an encoded serial bit stream of address and data bits of a PCI bus transaction.  
     
     
       46. The computer of claim 45 wherein the connector further conveys digital video display signals through a differential signal channel, and the connector is configured for coupling to a console through a cable.  
     
     
       47. The computer of claim 42 further comprising a mass storage device directly coupled to the central processing unit, wherein the mass storage device comprises flash memory.  
     
     
       48. A computer system comprising:
 a central processing unit (CPU) comprising an interface controller;   a first low voltage differential signal (LVDS) channel directly extending from the interface controller, the first LVDS channel comprising two unidirectional, serial bit channels to convey data in opposite directions, wherein each serial bit channel comprises four or more differential signal pairs; and   a second LVDS channel coupled to a connector, comprising two sets of unidirectional, serial bit channels to convey data in opposite directions;   wherein the first LVDS channel conveys encoded serial bit streams of address bits, data bits, and byte enable information bits of Peripheral Component Interconnect (“PCI”) bus transactions.    
     
     
       49. The computer system of claim 48 wherein the interface controller is coupled to Phase-Locked Loop (PLL) clock circuitry, and wherein the interface controller generates different data transfer rates to convey PCI bus transactions through the first LVDS channel based on different clock frequencies generated by the PLL clock circuitry.  
     
     
       50. The computer system of claim 49 wherein the second LVDS channel communicates Ethernet protocol traffic.  
     
     
       51. A computer system comprising:
 a central processing unit (CPU);   a peripheral bridge directly coupled to the CPU without any intervening Peripheral Component Interconnect (PCI) bus;   a first low voltage differential signal (LVDS) channel directly coupled to the peripheral bridge, comprising two unidirectional, serial bit channels to convey data in opposite directions, wherein each serial bit channels comprises four or more differential signal pairs; and   a second LVDS channel extending directly from the CPU, comprising two sets of unidirectional, serial bit channels to convey data in opposite directions;   wherein the first LVDS channel conveys encoded serial bit streams of address bits, data bits, and byte enable information bits of PCI bus transactions.    
     
     
       52. The computer system of claim 51 wherein the peripheral bridge comprises an interface controller coupled to Phase-Locked Loop (PLL) clock circuitry, and wherein the interface controller directly couples to the first LVDS channel to convey said PCI bus transactions.  
     
     
       53. The computer system of claim 52 wherein the interface controller generates different data transfer rates to convey said PCI bus transactions through the first LVDS channel based on different clock frequencies generated by the PLL clock circuitry.  
     
     
       54. A computer system comprising:
 a central processing unit (CPU) comprising an interface controller;   a first low voltage differential signal (LVDS) channel directly extending from the interface controller, the first LVDS channel comprising two unidirectional, serial bit channels to convey data in opposite directions, wherein each serial bit channel comprises four or more differential signal pairs; and   a second LVDS channel coupled to a connector, comprising two sets of unidirectional, serial bit channels to convey data in opposite directions; and   wherein the first LVDS channel conveys an encoded serial bit stream of address and data bits of a Peripheral Component Interconnect (“PCI”) bus transaction.    
     
     
       55. The computer system of claim 54 wherein the interface controller is coupled to Phase-Locked Loop (PLL) clock circuitry, and wherein the interface controller generates different data transfer rates to convey the PCI bus transaction through the first LVDS channel based on different clock frequencies generated by the PLL clock circuitry.  
     
     
       56. The computer system of claim 55 wherein the second LVDS channel communicates Ethernet protocol.  
     
     
       57. A computer system comprising:
 a central processing unit (CPU);   a peripheral bridge directly coupled to the CPU without any intervening Peripheral Component Interconnect (PCI) bus;   a first low voltage differential signal (LVDS) channel directly coupled to the peripheral bridge, comprising two unidirectional, serial bit channels to convey data in opposite directions, wherein each serial bit channel comprises four or more differential signal pairs; and   a second LVDS channel extending directly from the CPU, comprising two sets of unidirectional, serial bit channels to convey data in opposite directions;   wherein the first LVDS channel conveys an encoded serial bit stream of address and data bits of a PCI bus transaction.    
     
     
       58. The computer system of claim 57 wherein the peripheral bridge comprises an interface controller coupled to Phase-Locked Loop (PLL) clock circuitry, and wherein the interface controller is directly coupled to the first LVDS channel to convey said PCI bus transaction.  
     
     
       59. The computer system of claim 58 wherein the interface controller generates different data transfer rates to convey the PCI bus transaction through the LVDS channel based on different clock frequencies generated by the PLL clock circuitry.  
     
     
       60. A computer comprising:
 a connector for external peripheral data communication;   a central processing unit (CPU);   a first Low Voltage Differential Signal (LVDS) channel directly connected to the CPU comprising two unidirectional, serial bit channels that transmit data in opposite directions; and   a second LVDS channel to convey Universal Serial Bus (USB) protocol traffic through the connector, the second LVDS channel including two unidirectional, serial bit channels that transmit data in opposite direction; and   wherein the connector further conveys digital video data through a third differential signal channel.    
     
     
       61. The computer of claim 60 wherein the first LVDS channel conveys address and data bits, and byte enable information bits of a Peripheral Component Interconnect (PCI) bus transaction in serial form.  
     
     
       62. A computer comprising:
 a connector for external peripheral data communication;   an integrated central processing unit and graphics subsystem in a single chip; and   a first Low Voltage Differential Signal (LVDS) channel comprising two unidirectional, serial bit channels that transmit data in opposite directions;   wherein the integrated graphics subsystem directly outputs digital video display data to a unidirectional differential signal channel;   wherein the first LVDS channel conveys Universal Serial Bus (USB) protocol traffic through the connector and wherein the digital video display data couples to the connector.    
     
     
       63. The computer of claim 62 wherein the digital video display data is transmitted through Transition Minimized Differential Signaling (TMDS).