USRE46749EActiveUtility

Method for controlling a non-volatile semiconductor memory device

79
Assignee: TOSHIBA MEMORY CORPPriority: Sep 14, 2007Filed: Mar 28, 2013Granted: Mar 6, 2018
Est. expirySep 14, 2027(~1.1 yrs left)· nominal 20-yr term from priority
Inventors:Koji Hosono
G11C 16/0483G11C 16/3418G11C 11/5642G11C 16/3454G11C 2211/565G11C 16/26G11C 16/02G11C 16/34
79
PatentIndex Score
4
Cited by
33
References
38
Claims

Abstract

A non-volatile semiconductor memory device has a NAND string, in which multiple memory cells are connected in series. A read procedure is performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a selected voltage while unselected memory cells are driven to be turned on without regard to cell data thereof. In the read procedure, a first read pass voltage is applied to unselected memory cells except an adjacent and unselected memory cell disposed adjacent to the selected memory cell, the adjacent and unselected memory cell being completed in data write later than the selected memory cell, and a second read pass voltage higher than the first read pass voltage is applied to the adjacent and unselected memory cell.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A method for controlling a non-volatile semiconductor memory device having a NAND string, in which multiple memory cells are connected in series, comprising:
 a read procedure performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a selected voltage while unselected memory cells are driven to be turned on without regard to cell data thereof, wherein 
 a first read pass voltage and a second read pass voltage higher than the first read pass voltage are generated by a voltage generation circuit, and wherein 
 the first read pass voltage generated by the voltage generation circuit is applied to unselected memory cells except adjacent and unselected memory cells disposed adjacent to the selected memory cell, and the second read pass voltage generated by the voltage generation circuit is applied to at least one of the adjacent and unselected memory cells in the read procedure. 
 
     
     
       2. The method according to  claim 1 , wherein
 the second read pass voltage is applied to the adjacent and unselected memory cell being completed in data write later than the selected memory cell. 
 
     
     
       3. The method according to  claim 1 , wherein
 the read procedure is a normal read procedure for reading data of the selected memory cell after data writing. 
 
     
     
       4. The method according to  claim 1 , wherein
 the read procedure is a write-verify read procedure for verify-reading data of the selected memory cell in a data write mode. 
 
     
     
       5. The method according to  claim 3 , wherein
 in the normal read procedure, the second read pass voltage is applied to one cell in two adjacent and unselected memory cells disposed adjacent to the selected memory cell, the one cell having been written previously to the selected memory cell; and a third pass voltage is applied to the other cell in the two adjacent and unselected memory cells, the other cell having been written later than the selected memory cell, the third read pass voltage being selected in level in accordance with the cell's threshold shift amount. 
 
     
     
       6. The method according to  claim 5 , wherein
 the third read pass voltage is set to be lower than the first read pass voltage in case the cell's threshold shift amount is less than a certain level while the third read pass voltage is set to be equal to the second read pass voltage in case the cell's threshold shift amount is greater than the certain level. 
 
     
     
       7. The method according to  claim 5 , wherein
 the normal read procedure includes: 
 a first read operation performed for reading data of the other cell previously to reading data of the selected memory cell when it is selected; and 
 a second read operation performed for reading data of the selected memory cell on the condition that the third read pass voltage is selected in level with reference to the read data of the first read operation. 
 
     
     
       8. The method according to  claim 1 , wherein
 the memory cell stores four-level data defined by data level E, A, B and C (where, E<A<B<C), data level E being defined as an erase state with a negative cell threshold while data levels A, B and C are defined as write states with positive cell threshold voltages, and 
 a data write procedure includes: a lower page write mode for selectively writing the memory cells with data level E to have a medium level LM set between data level A and B; and an upper page write mode for selectively writing the memory cells with data level E and data level LM to have data level A and data level B or C, respectively, and 
 in the data write procedure, the memory cells in the NAND string are selected from a source line side in such an order that a first memory cell is written in a lower page write mode; a second memory cell adjacent to the first memory cell disposed adjacent to the first memory cell on a bit line side is written in the successive lower page write mode; and then the first memory cell is written in an upper page write mode. 
 
     
     
       9. A method for controlling a non-volatile semiconductor memory device having a NAND string, in which multiple memory cells are connected in series, comprising:
 a write-verifying procedure performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a write-verifying voltage and unselected memory cells are driven to be turned on without regard to cell data thereof; and 
 a normal read procedure performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a read voltage and unselected memory cells are driven to be turned on without regard to cell data thereof, wherein 
 in the write-verifying procedure, a first read pass voltage is applied to unselected memory cells except two adjacent and unselected memory cells disposed adjacent to the selected memory cell; a second read pass voltage higher than the first read pass voltage is applied to one cell of the two adjacent and unselected memory cells, the one cell having been written previously to the selected memory cell; and a third read pass voltage lower than the first read pass voltage is applied to the other cell, which is written later than the selected memory cell, and 
 in the normal read procedure, the first read pass voltage is applied to the unselected memory cells except the two adjacent and unselected memory cells; the second read pass voltage higher than the first read pass voltage is applied to one cell of the two adjacent and unselected memory cells, the one cell having been written previously to the selected memory cell; and a fourth read pass voltage is applied to the other cell, which has been written later than the selected memory cell, the fourth read pass voltage being selected in level in accordance with the cell's threshold shift amount. 
 
     
     
       10. The method according to  claim 9 , wherein
 the fourth read pass voltage is set to be lower than the first read pass voltage in case the cell's threshold shift amount is less than a certain level while the fourth read pass voltage is set to be equal to the second read pass voltage in case the cell's threshold shift amount is greater than the certain level. 
 
     
     
       11. The method according to  claim 10 , wherein
 the normal read procedure includes: 
 a first read operation performed for reading data of the other cell previously to reading data of the selected memory cell when it is selected; and 
 a second read operation performed for reading data of the selected memory cell on the condition that the fourth read pass voltage is selected in level with reference to the read data of the first read operation. 
 
     
     
       12. The method according to  claim 9 , wherein
 the memory cell stores four-level data defined by data level E, A, B and C (where, E<A<B<C), data level E being defined as an erase state with a negative cell threshold while data levels A, B and C are defined as write states with positive cell threshold voltages, and 
 a data write procedure includes: a lower page write mode for selectively writing the memory cells with data level E to have a medium level LM set between data level A and B; and an upper page write mode for selectively writing the memory cells with data level E and data level LM to have data level A and data level B or C, respectively, and 
 in the data write procedure, the memory cells in the NAND string are selected from a source line side in such an order that a first memory cell is written in a lower page write mode; a second memory cell adjacent to the first memory cell disposed adjacent to the first memory cell on a bit line side is written in a successive lower page write mode; and then the first memory cell is written in an upper page write mode. 
 
     
     
       13. A method for controlling a non-volatile semiconductor memory device having a NAND string, in which multiple memory cells are connected in series, comprising:
 a write-verifying procedure performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a write-verifying voltage and unselected memory cells are driven to be turned on without regard to cell data thereof; and 
 a normal read procedure performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a read voltage and unselected memory cells are driven to be turned on without regard to cell data thereof, wherein 
 in the write-verifying procedure, a first read pass voltage is applied to unselected memory cells except adjacent and unselected memory cells adjacent to the selected memory cell; a second read pass voltage lower than the first read pass voltage is applied to one of the adjacent and unselected memory cells, which is written later than the selected memory cell, and 
 in the normal read procedure, the first read pass voltage is applied to the unselected memory cells except the adjacent and unselected memory cells disposed adjacent to the selected memory cell; a third read pass voltage is applied to one of the adjacent and unselected memory cells, which has been written later than the selected memory cell, the third read voltage being selected in level in accordance with the cell's threshold shift amount, the maximum vale of which is higher than the first read pass voltage. 
 
     
     
       14. The method according to  claim 13 , wherein
 the memory cell stores four-level data defined by data level E, A, B and C (where, E<A<B<C), data level E being defined as an erase state with a negative cell threshold while data levels A, B and C are defined as write states with positive cell threshold voltages, and 
 a data write procedure includes: a lower page write mode for selectively writing the memory cells with data level E to have a medium level LM set between data level A and B; and an upper page write mode for selectively writing the memory cells with data level E and data level LM to have data level A and data level B or C, respectively, and 
 in the data write procedure, the memory cells in the NAND string are selected from a source line side in such an order that a first memory cell is written in a lower page write mode; a second memory cell adjacent to the first memory cell disposed adjacent to the first memory cell on a bit line side is written in a successive lower page write mode; and then the first memory cell is written in an upper page write mode. 
 
     
     
       15. A method for controlling a non-volatile semiconductor memory device having a NAND string, in which multiple memory cells are connected in series, comprising:
 a write-verifying procedure performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a write-verifying voltage and unselected memory cells are driven to be turned on without regard to cell data thereof; and 
 a normal read procedure performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a read voltage and unselected memory cells are driven to be turned on without regard to cell data thereof, wherein 
 in the write-verifying procedure, a first read pass voltage is applied to unselected memory cells except adjacent and unselected memory cells adjacent to the selected memory cell; a second read pass voltage lower than the first read pass voltage is applied to one of the adjacent and unselected memory cells, which is written later than the selected memory cell, and 
 in the normal read procedure, the first read pass voltage is applied to the unselected memory cells except the adjacent and unselected memory cells disposed adjacent to the selected memory cell; a third read pass voltage is applied to one of the adjacent and unselected memory cells, which has been written later than the selected memory cell, the third read voltage being selected in level in accordance with the cell data, the maximum value of which is higher than the first read pass voltage. 
 
     
     
       16. The method according to  claim 15 , wherein
 the memory cell stores multi-level data defined as a cell threshold voltage, and 
 in a data write procedure, the memory cells in the NAND strings are selected in order from a source line side, and the multi-level data writing are completed for each selected memory cell. 
 
     
     
       17. A method for controlling a non-volatile semiconductor memory device including a NAND string, in which multiple memory cells are connected in series, comprising:
 a read procedure performed for a selected memory cell in the NAND string on the condition that a selected voltage is applied to a selected word line and unselected voltages are applied to unselected word lines, the selected word line being connected to the selected memory cell, the unselected word lines being connected to unselected memory cells and including first unselected word lines and second unselected word lines, the first unselected word lines being adjacent to the selected word line, the second unselected word lines including an unselected word line disposed adjacent to one of the first unselected word lines, the unselected voltages including a first voltage and a second voltage, the second voltage being higher than the first voltage, both the first voltage and the second voltage being generated by a voltage generation circuit, and   wherein the first voltage generated by the voltage generation circuit is applied to the second unselected word lines, and the second voltage generated by the voltage generation circuit is applied to one of the first unselected word lines.    
     
     
       18. The method according to claim 17, wherein
 the multiple memory cells include a first memory cell and a second memory cell, the first memory cell being disposed adjacent to the second memory cell, the first and second memory cell being capable of holding four-level data defined by data level E, A, B and C (where, E<A<B<C), and   a write procedure including a lower page write mode and an upper page write mode is executed, the lower page write mode including a first lower page write mode and a second lower page write mode, the first lower page write mode being executed to the first memory cell, the second lower page write mode being executed to the second memory cell after the first lower page write mode, the upper page write mode being executed to the first memory cell after the second lower page write mode.    
     
     
       19. The method according to claim 18, wherein
 the read procedure is a normal read procedure for reading data of the selected memory cell after data writing.    
     
     
       20. The method according to claim 18, wherein
 the read procedure is a write-verify read procedure for verify-reading data of the selected memory cell in the lower page write mode or the upper page write mode.    
     
     
       21. The method according to claim 17, wherein
 the NAND string includes a first transistor and a second transistor, the first transistor being connected to a bit line, the second transistor being connected to a source line,   a third voltage is applied to a gate of the first transistor in the read procedure,   a fourth voltage is applied to a gate of the second transistor in the read procedure, and   the fourth voltage is applied to the gate of the second transistor after applying the first voltage, the second voltage, and the third voltage.    
     
     
       22. The method according to claim 18, wherein
 the NAND string includes a first transistor and a second transistor, the first transistor being connected to a bit line, the second transistor being connected to a source line,   a third voltage is applied to a gate of the first transistor in the read procedure,   a fourth voltage is applied to a gate of the second transistor in the read procedure, and   the fourth voltage is applied to the gate of the second transistor after applying the first voltage, the second voltage, and the third voltage.    
     
     
       23. A method for controlling a non-volatile semiconductor memory device including a NAND string, in which first to n-th memory cells (n is a natural number and is equal to or more than 2) are connected in series, first to n-th word lines being electrically connected to the first to n-th memory cells, comprising:
 a read procedure performed for k-th memory cell (k is a natural number and range of k is from 3 to n−2) in the NAND string on the condition that a selected voltage is applied to the k-th word line, a first voltage is applied to both (k−1)-th word line and (k+1)-th word line, and a second voltage is applied to both (k−2)-th word line and (k+2)-th word line, the first voltage being higher than the second voltage, both the first voltage and the second voltage being generated by a voltage generation circuit.    
     
     
       24. The method according to claim 23, wherein
 the first to n-th memory cells being capable of holding four-level data defined by data level E, A, B and C (where, E<A<B<C), and   a write procedure including a lower page write mode and an upper page write mode is executed, the lower page write mode including a first lower page write mode and a second lower page write mode, the first lower page write mode being executed to the k-th memory cell, the second lower page write mode being executed to (k+1)-th memory cell after the first lower page write mode, the upper page write mode being executed to the k-th memory cell after the second lower page write mode.    
     
     
       25. The method according to claim 23, wherein
 the read procedure is a normal read procedure for reading data of the k-th memory cell after data writing.    
     
     
       26. The method according to claim 23, wherein
 the NAND string includes a first transistor and a second transistor, the first transistor being connected to a bit line, the second transistor being connected to a source line,   a third voltage is applied to a gate of the first transistor in the read procedure,   a fourth voltage is applied to a gate of the second transistor in the read procedure, and   the fourth voltage is applied to the gate of the second transistor after applying the first voltage, the second voltage, and the third voltage.    
     
     
       27. The method according to claim 24, wherein
 the NAND string includes a first transistor and a second transistor, the first transistor being connected to a bit line, the second transistor being connected to a source line,   a third voltage is applied to a gate of the first transistor in the read procedure,   a fourth voltage is applied to a gate of the second transistor in the read procedure, and   the fourth voltage is applied to the gate of the second transistor after applying the first voltage, the second voltage, and the third voltage.    
     
     
       28. A non-volatile semiconductor memory device comprising:
 a NAND string including first to n-th memory cells (n is a natural number and is equal to or more than 2), the first to n-th memory cells being connected in series,   first to n-th word lines electrically connected to the first to n-th memory cells,   a controller configured to apply a selected voltage to a k-th word line(k is a natural number and range of k is from 3 to n−2), apply a first voltage to both (k−1)-th word line and (k+1)-th word line, and apply a second voltage to both (k−2)-th word line and (k+2)-th word line in a read procedure, the first voltage being higher than the second voltage, both the first voltage and the second voltage being generated by a voltage generation circuit.    
     
     
       29. The non-volatile semiconductor memory device according to claim 28, wherein
 the first to n-th memory cells are capable of holding four-level data defined by data level E, A, B and C (where, E<A<B<C).    
     
     
       30. The non-volatile semiconductor memory device according to claim 28, wherein
 the NAND string includes a first transistor and a second transistor, the first transistor being connected to a bit line, the second transistor being connected to a source line,   a third voltage is applied to a gate of the first transistor in the read procedure,   a fourth voltage is applied to a gate of the second transistor in the read procedure, and   the fourth voltage is applied to the gate of the second transistor after applying the first voltage, the second voltage, and the third voltage.    
     
     
       31. A non-volatile semiconductor memory device comprising:
 a NAND string including first to n-th memory cells (n is a natural number and is equal to or more than 2), the first to n-th memory cells being connected in series,   first to n-th word lines electrically connected to the first to n-th memory cells,   a voltage generation circuit configured to generate a selected voltage, a first voltage, and a second voltage, wherein   the selected voltage is applied to the k-th word line(k is a natural number and range of k is from 3 to n−2), the first voltage is applied to both (k−1)-th word line and (k+1)-th word line, and the second voltage is applied to both (k−2)-th word line and (k+2)-th word line when a read procedure is executed, the first voltage being higher than the second voltage.    
     
     
       32. The non-volatile semiconductor memory device according to claim 31, wherein
 the first to n-th memory cells are capable of holding four-level data defined by data level E, A, B and C (where, E<A<B<C).    
     
     
       33. The non-volatile semiconductor memory device according to claim 31, wherein
 the NAND string includes a first transistor and a second transistor, the first transistor being connected to a bit line, the second transistor being connected to a source line,   a third voltage is applied to a gate of the first transistor in the read procedure,   a fourth voltage is applied to a gate of the second transistor in the read procedure, and   the fourth voltage is applied to the gate of the second transistor after applying the first voltage, the second voltage, and the third voltage.    
     
     
       34. The method according to claim 17, wherein
 the second unselected word lines include an unselected word line disposed adjacent to the other of the first unselected word lines.    
     
     
       35. A method for controlling a non-volatile semiconductor memory device including a NAND string, in which multiple memory cells are connected in series, comprising:
 a read procedure performed for a selected memory cell in the NAND string on the condition that a selected voltage is applied to a selected word line and unselected voltages are applied to unselected word lines, the selected word line being connected to the selected memory cell, the unselected word lines being connected to unselected memory cells, the unselected voltages including a first voltage and a second voltage, the second voltage being higher than the first voltage, both the first voltage and the second voltage being generated by a voltage generation circuit, and   wherein the first voltage generated by the voltage generation circuit is applied to the unselected word lines except adjacent and unselected word lines disposed adjacent to the selected word line, and the second voltage generated by the voltage generation circuit is applied to at least one of the adjacent and unselected word lines,   wherein the multiple memory cells include a first memory cell and a second memory cell, the first memory cell being disposed adjacent to the second memory cell, the first and second memory cell being capable of holding four-level data defined by data level E, A, B and C (where, E<A<B<C), and   wherein a write procedure including a lower page write mode and an upper page write mode is executed, the lower page write mode including a first lower page write mode and a second lower page write mode, the first lower page write mode being executed to the first memory cell, the second lower page write mode being executed to the second memory cell after the first lower page write mode, the upper page write mode being executed to the first memory cell after the second lower page write mode.    
     
     
       36. The method according to claim 35, wherein
 the read procedure is a normal read procedure for reading data of the selected memory cell after data writing.    
     
     
       37. The method according to claim 35, wherein
 the read procedure is a write-verify read procedure for verify-reading data of the selected memory cell in the lower page write mode or the upper page write mode.    
     
     
       38. The method according to claim 35, wherein
 the NAND string includes a first transistor and a second transistor, the first transistor being connected to a bit line, the second transistor being connected to a source line,   a third voltage is applied to a gate of the first transistor in the read procedure,   a fourth voltage is applied to a gate of the second transistor in the read procedure, and   the fourth voltage is applied to the gate of the second transistor after applying the first voltage, the second voltage, and the third voltage.

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