Programming method for non-volatile memory device

Abstract

Provided is a method of programming a non-volatile memory device. The method includes applying a first programming pulse to a corresponding wordline of the non-volatile memory device, applying a second programming pulse to the wordline, wherein a voltage of the second programming pulse is different from that of the first programming pulse, and applying voltages to each bitline connected to the wordline, the voltages applied to each of the bitlines are different from each other according to a plurality of bit values to be programmed to corresponding memory cells in response to the first programming pulse or the second programming pulse.

What is claimed is: 
     
       1. A method of programming memory cells of a multi-level cell non-volatile memory to one of a plurality of data values, the method comprising:
 applying a first programming pulse to a wordline of the non-volatile memory device and a first bitline voltage to at least one first bitline associated with the wordline corresponding to a first data value among a plurality of data values;   applying a second programming pulse to the wordline, a second bitline voltage to at least one second bitline associated with the wordline corresponding to a second data value among the plurality of data values, and a third bitline voltage to at least one third bitline associated with the wordline corresponding to a third data value among the plurality of data values,   wherein a voltage level of the second programming pulse is different from a level of the first programming pulse,   the second bitline voltage is different from the third bitline voltage if the second data value and third data value are different,   the second bitline voltage is applied to the at least one second bitline and the third bitline voltage is applied to the at least one third bitline simultaneously, and   a time interval required to apply both the first programming pulse and the second programming pulse to the wordline is sufficiently small to preclude substantial capacitive coupling between physically proximate memory cells in the nonvolatile memory device.   
     
     
       2. The method of  claim 1 , wherein the second programming pulse is applied to the wordline after the first programming pulse. 
     
     
       3. The method of  claim 2 , further comprising:
 after applying the second programming pulse, applying at least one of a sequence of verifying voltages to the respective bitlines, wherein a level of the at least one of the sequence of verifying voltages varies in accordance with the data value to be programmed to the memory cell.   
     
     
       4. The method of  claim 3 , wherein respective levels of the verifying voltages in the sequence of verifying voltages sequentially increase, as applied during the verifying operation. 
     
     
       5. The method of  claim 3 , wherein each one of the respective levels of the verifying voltages in the sequence of verifying voltages is_less than levels of the first programming pulse and the second programming pulse. 
     
     
       6. The method of  claim 3 , wherein the method of programming the multi-level cell non-volatile memory device is an iterative method comprising multiple programming loops, wherein each programming loop comprises:
 applying the first programming pulse to the wordline and the first bitline voltage to the at least one first bitline, and then applying the second programming pulse to the wordline and the second bitline voltage to the at least one second bitline and the third bitline voltage to the at least one third bitline voltage, and then applying the at least one of the sequence of verifying voltages to the bitline.   
     
     
       7. The method of  claim 6 , wherein the level of the first programming pulse and the level of the second programming pulse respectively increase with each successive iteration of the programming loop. 
     
     
       8. The method of  claim 1 , wherein the level of the first programming pulse is less than the level of the second programming pulse. 
     
     
       9. A method of programming a non-volatile memory device comprising a first memory cell connected to a wordline and a first bitline and a second memory cell connected to the wordline and a second bitline, wherein the first memory cell and second memory cell are multi-level non-volatile memory cells capable of being programmed to 1 st  through M th  data values, the method comprising:
 performing a programming operation during which the first memory cell is programmed to an i th  data value among the 1 st  through M th  data values using a first programming pulse applied to the wordline, and the second memory cell is programmed to a j th  data value among the 1 st  through M th  data values using a second programming pulse different from the first programming pulse and applied to the wordline, the programming operation comprising:   simultaneously applying a first bitline voltage having a first level and corresponding to the i th  data value to the first bitline, and a second bitline voltage having a second level different from the first level and corresponding to the j th  data value to the second bitline; and   performing a verifying operation on the first memory cell and second memory cell, wherein execution timing for the verifying operation varies in relation to the 1 st  through M th  data values,   wherein a time interval required to apply both the first programming pulse and the second programming pulse to the wordline is sufficiently small to preclude substantial capacitive coupling between either the first memory cell and the second memory and at least one other memory cell physically proximate to the at least one of the first memory cell and the second memory cell.   
     
     
       10. The method of  claim 9 , wherein the verifying operation comprises:
 applying at least one of a sequence of verifying voltages to the first and second bitlines, wherein respective levels of the sequence of verifying voltages vary in accordance with a corresponding one of the 1 st  through M th  data values.   
     
     
       11. The method of  claim 9 , wherein the programming operation programs the i th  data value before programming the j th  data value, and
 the verifying operation comprises applying up to a first number of verifying voltages to verify the programming of the i th  data value and applying up to a second number of verifying voltages to verify the programming of the j th  data value, wherein the first number is greater than the second number.   
     
     
       12. The method of  claim 11 , wherein applying up to the first number of verifying voltages requires up to a first execution time, and applying up to the second number of verifying voltages requires up to a second execution time, wherein the first execution time is greater than the second execution time. 
     
     
       13. An iterative method of programming memory cells of a multi-level cell non-volatile memory to one of a plurality of data values, the iterative method comprising multiple programming loops, wherein each programming loop comprises:
 applying a first programming pulse to a wordline of the non-volatile memory device, and applying a first bitline voltage corresponding to a first data value among a plurality of data values to a first bitline;   applying a second programming pulse having a level different from a level of the first programming pulse to the wordline after applying the first programming pulse to the wordline, and applying a second bitline voltage corresponding to a second data value among the plurality of data values to a second bitline, and applying a third bitline voltage corresponding to a third data value among the plurality of data values to a third bitline, wherein the second bitline voltage is applied to the second bitline and the third bitline voltage is applied to the third bitline simultaneously, wherein the second bitline voltage is different from the third bitline voltage if the second data value and third data value are different; and   after applying the second programming pulse, applying at least one of a sequence of verifying voltages to the first bitline and the second bitline, wherein a level of the at least one of the sequence of verifying voltages varies in accordance with a data value being programmed to the memory cell.   
     
     
       14. The method of  claim 13 , wherein the level of the first programming pulse and the level of the second programming pulse respectively increase with each successive iteration of the programming loop. 
     
     
       15. A method of programming memory cells of a multi-level cell non-volatile memory device to one of a plurality of data values, the method comprising:
 performing a first program loop; and   performing a second program loop;   wherein the first program loop comprising:
 during a first program time, applying a first programming pulse to a wordline connected to selected memory cells among the memory cells of the multi-level cell non-volatile memory device and a first bitline voltage to at least one first bitline connected to at least one first memory cell among the selected memory cells associated with the wordline corresponding to a first data value among the plurality of data values; and 
 during a second program time, applying a second programming pulse to the wordline, a second bitline voltage to at least one second bitline connected to at least one second memory cell among the selected memory cells associated with the wordline corresponding to a second data value among the plurality of data values, and a third bitline voltage to at least one third bitline connected to at least one third memory cell among the selected memory cells associated with the wordline corresponding to a third data value among the plurality of data values, 
   wherein a voltage level of the second programming pulse is different from a voltage level of the first programming pulse,   a level of the second bitline voltage is different from a level of the third bitline voltage if the second data value and the third data value are different,   each of a level of the first bitline voltage, the level of the second bitline voltage and the level of the third bitline voltage is lower than a level of a program inhibit voltage,   the second bitline voltage is applied to the at least one second bitline and the third bitline voltage is applied to the at least one third bitline simultaneously;   physically proximate memory cells connected to the wordline in the multi-level cell nonvolatile memory device include the at least one first memory cell and at least one other memory cell adjacent to the at least one first memory cell;   the first programming pulse and the second programming pulse are successively applied to the wordline.   
     
     
       16. The method of claim 15, wherein the second program loop comprising:
 applying the first programming pulse to the wordline; and   applying the second programming pulse to the wordline.   
     
     
       17. The method of claim 15, wherein, during the first program time, applying the program inhibit voltage to the at least one second bitline and the at least one third bitline concurrently with the applying the first bitline voltage to the at least one first bitline. 
     
     
       18. The method of claim 16, wherein, during the second program time, applying the program inhibit voltage to the at least one first bitline concurrently with the applying the second bitline voltage to the at least one second bitline. 
     
     
       19. The method of claim 15, wherein a first programming operation corresponding to the first data value and at least one of a second programming operation corresponding to the second data value and a third programming operation corresponding to the third data value are completed in a same program loop. 
     
     
       20. The method of claim 15, wherein the second programming pulse is applied to the wordline after the applying the first programming pulse. 
     
     
       21. The method of claim 15, wherein during a verification time after the applying the first programming pulse and the applying the second programming pulse, a first verification pulse, a second verification pulse and a third verification pulse are applied to the wordline successively. 
     
     
       22. The method of claim 21, wherein a voltage level of the first verification pulse is lower than a voltage level of the second verification pulse, and
 the voltage level of the second verification pulse is lower than a voltage level of the third verification pulse.   
     
     
       23. A method of programming memory cells of a multi-level cell non-volatile memory device to one of a plurality of data values, the method comprising:
 during a first program time, applying a first programming pulse to a wordline connected to selected memory cells among the memory cells of the multi-level cell non-volatile memory device and a first bitline voltage to at least one first bitline connected to at least one first memory cell among the selected memory cells associated with the wordline corresponding to a first data value among the plurality of data values;   during a second program time, applying a second programming pulse to the wordline, a second bitline voltage to at least one second bitline connected to at least one second memory cell among the selected memory cells associated with the wordline corresponding to a second data value among the plurality of data values, and a third bitline voltage to at least one third bitline connected to at least one third memory cell among the selected memory cells associated with the wordline corresponding to a third data value among the plurality of data values; and   during a verification time after the applying the first programming pulse and the second programming pulse, applying successively, to the wordline, a first wordline verification pulse corresponding to the first data value, a second wordline verification pulse corresponding to the second data value and a third wordline verification pulse corresponding to the third data value,   wherein a voltage level of the second programming pulse is different from a voltage level of the first programming pulse,   a level of the second bitline voltage is different from a level of the third bitline voltage if the second data value and the third data value are different,   each of a level of the first bitline voltage, the level of the second bitline voltage and the level of the third bitline voltage is lower than a level of a program inhibit voltage,   the second bitline voltage is applied to the at least one second bitline and the third bitline voltage is applied to the at least one third bitline simultaneously;   physically proximate memory cells connected to the wordline in the multi-level cell nonvolatile memory device include the at least one first memory cell and at least one other memory cell adjacent to the at least one first memory cell;   the first programming pulse and the second programming pulse are successively applied.   
     
     
       24. The method of claim 23, wherein, during the first program time, applying the program inhibit voltage to the at least one second bitline and the at least one third bitline concurrently with the applying the first bitline voltage to the at least one first bitline. 
     
     
       25. The method of claim 24, wherein, during the second program time, applying the program inhibit voltage to the at least one first bitline concurrently with the applying the second bitline voltage to the at least one second bitline. 
     
     
       26. The method of claim 23, wherein a first programming operation corresponding to the first data value and at least one of a second programming operation corresponding to the second data value and a third programming operation corresponding to the third data value are completed substantially simultaneously. 
     
     
       27. The method of claim 23, wherein a first programming operation corresponding to the first data value and at least one of a second programming operation corresponding to the second data value and a third programming operation corresponding to the third data value are completed at a same program loop. 
     
     
       28. The method of claim 23, wherein the second programming pulse is applied to the wordline after the applying the first programming pulse. 
     
     
       29. The method of claim 23, wherein the first wordline verification pulse, the second wordline verification pulse and the third wordline verification pulse are applied to the wordline successively. 
     
     
       30. The method of claim 29, wherein a voltage level of the first wordline verification pulse is lower than a voltage level of the second wordline verification pulse, and
 the voltage level of the second wordline verification pulse is lower than a voltage level of the third wordline verification pulse.   
     
     
       31. A method of programming memory cells of a multi-level cell non-volatile memory device to one of a plurality of data values, the method comprising:
 during a first program time, applying a first programming pulse to a wordline connected to selected memory cells among the memory cells of the multi-level cell non-volatile memory device and a first bitline voltage to at least one first bitline connected to at least one first memory cell among the selected memory cells associated with the wordline corresponding to a first data value among the plurality of data values;   during a second program time, applying a second programming pulse to the wordline, a second bitline voltage to at least one second bitline connected to at least one second memory cell among the selected memory cells associated with the wordline corresponding to a second data value among the plurality of data values, and a third bitline voltage to at least one third bitline connected to at least one third memory cell among the selected memory cells associated with the wordline corresponding to a third data value among the plurality of data values; and   during a verification time after the applying the first programming pulse and the second programming pulse, applying successively, to the wordline, a first wordline verification pulse corresponding to the first data value, a second wordline verification pulse corresponding to the second data value and a third wordline verification pulse corresponding to the third data value,   wherein a voltage level of the second programming pulse is different from a voltage level of the first programming pulse,   a level of the second bitline voltage is different from a level of the third bitline voltage if the second data value and the third data value are different,   each of a level of the first bitline voltage, the level of the second bitline voltage and the level of the third bitline voltage is lower than a level of a program inhibit voltage,   the second bitline voltage is applied to the at least one second bitline and the third bitline voltage is applied to the at least one third bitline simultaneously;   physically proximate memory cells connected to the wordline in the multi-level cell nonvolatile memory device include the at least one second memory cell and at least one other memory cell adjacent to the at least one first memory cell;   the first programming pulse and the second programming pulse are successively applied.   
     
     
       32. The method of claim 31, wherein, during the first program time, applying the program inhibit voltage to the at least one second bitline and the at least one third bitline concurrently with the applying the first bitline voltage to the at least one first bitline. 
     
     
       33. The method of claim 32, wherein, during the second program time, applying the program inhibit voltage to the at least one first bitline concurrently with the applying the second bitline voltage to the at least one second bitline. 
     
     
       34. The method of claim 31, wherein a first programming operation corresponding to the first data value and at least one of a second programming operation corresponding to the second data value and a third programming operation corresponding to the third data value are completed substantially simultaneously. 
     
     
       35. The method of claim 31, wherein a first programming operation corresponding to the first data value and at least one of a second programming operation corresponding to the second data value and a third programming operation corresponding to the third data value are completed at a same program loop. 
     
     
       36. The method of claim 31, wherein the second programming pulse is applied to the wordline after the applying the first programming pulse. 
     
     
       37. The method of claim 31, wherein the first wordline verification pulse, the second wordline verification pulse and the third wordline verification pulse are applied to the wordline successively. 
     
     
       38. The method of claim 37, wherein a voltage level of the first wordline verification pulse is lower than a voltage level of the second wordline verification pulse, and
 the voltage level of the second wordline verification pulse is lower than a voltage level of the third wordline verification pulse.   
     
     
       39. A method of programming memory cells of a multi-level cell non-volatile memory device to one of a plurality of data values, the method comprising:
 during a first program time, applying a first programming pulse to a wordline connected to selected memory cells among the memory cells of the multi-level cell non-volatile memory device and a first bitline voltage to at least one first bitline connected to at least one first memory cell among the selected memory cells associated with the wordline, the at least one first bitline corresponding to a first data value among the plurality of data values;   during a second program time, applying a second programming pulse to the wordline, a second bitline voltage to at least one second bitline connected to at least one second memory cell among the selected memory cells associated with the wordline, the at least one second bitline corresponding to a second data value among the plurality of data values, and a third bitline voltage to at least one third bitline connected to at least one third memory cell among the selected memory cells associated with the wordline, the at least one third bitline corresponding to a third data value among the plurality of data values; and   during a verification time, applying, to the wordline, a first wordline verification pulse corresponding to the first data value, a second wordline verification pulse corresponding to the second data value and a third wordline verification pulse corresponding to the third data value,   wherein a voltage level of the second programming pulse is different from a voltage level of the first programming pulse,   a level of the second bitline voltage is different from a level of the third bitline voltage if the second data value and the third data value are different,   each of a level of the first bitline voltage, the level of the second bitline voltage and the level of the third bitline voltage is lower than a level of a program inhibit voltage,   the second bitline voltage is applied to the at least one second bitline and the third bitline voltage is applied to the at least one third bitline simultaneously,   physically proximate memory cells connected to the wordline in the multi-level cell nonvolatile memory device include the at least one first memory cell and at least one other memory cell adjacent to the at least one first memory cell, and   the first programming pulse and the second programming pulse are successively applied.   
     
     
       40. The method of claim 39, wherein, during the first program time, applying the program inhibit voltage to the at least one second bitline and the at least one third bitline concurrently with the applying the first bitline voltage to the at least one first bitline. 
     
     
       41. The method of claim 40, wherein, during the second program time, applying the program inhibit voltage to the at least one first bitline concurrently with the applying the second bitline voltage to the at least one second bitline. 
     
     
       42. The method of claim 40, wherein a first programming operation corresponding to the first data value, and at least one of a second programming operation corresponding to the second data value and a third programming operation corresponding to the third data value are completed substantially simultaneously. 
     
     
       43. The method of claim 40, wherein a first programming operation corresponding to the first data value, and at least one of a second programming operation corresponding to the second data value and a third programming operation corresponding to the third data value are completed at a same program loop. 
     
     
       44. The method of claim 39, wherein the second programming pulse is applied to the wordline after the applying the first programming pulse. 
     
     
       45. The method of claim 39, wherein the first wordline verification pulse, the second wordline verification pulse and the third wordline verification pulse are applied to the wordline successively. 
     
     
       46. The method of claim 45, wherein a voltage level of the first wordline verification pulse is lower than a voltage level of the second wordline verification pulse, and
 the voltage level of the second wordline verification pulse is lower than a voltage level of the third wordline verification pulse.   
     
     
       47. A method of programming memory cells of a multi-level cell non-volatile memory device to one of a plurality of data values, the method comprising:
 during a first program time, applying a first programming pulse to a wordline connected to selected memory cells among the memory cells of the multi-level cell non-volatile memory device and a first bitline voltage to at least one first bitline connected to at least one first memory cell among the selected memory cells associated with the wordline, the at least one first bitline corresponding to a first data value among the plurality of data values;   during a second program time, applying a second programming pulse to the wordline, a second bitline voltage to at least one second bitline connected to at least one second memory cell among the selected memory cells associated with the wordline, the at least one second bitline corresponding to a second data value among the plurality of data values, and a third bitline voltage to at least one third bitline connected to at least one third memory cell among the selected memory cells associated with the wordline, the at least one third bitline corresponding to a third data value among the plurality of data values; and   during a verification time after the applying the first programming pulse and the second programming pulse, applying, to the wordline, a first wordline verification pulse corresponding to the first data value, a second wordline verification pulse corresponding to the second data value and a third wordline verification pulse corresponding to the third data value,   wherein a voltage level of the second programming pulse is different from a voltage level of the first programming pulse,   a level of the second bitline voltage is different from a level of the third bitline voltage if the second data value and the third data value are different,   each of a level of the first bitline voltage, the level of the second bitline voltage and the level of the third bitline voltage is lower than a level of a program inhibit voltage,   the second bitline voltage is applied to the at least one second bitline and the third bitline voltage is applied to the at least one third bitline simultaneously,   physically proximate memory cells connected to the wordline in the multi-level cell nonvolatile memory device include the at least one first memory cell and at least one other memory cell adjacent to the at least one first memory cell, and   the first programming pulse and the second programming pulse are successively applied.   
     
     
       48. The method of claim 47, wherein, during the first program time, applying the program inhibit voltage to the at least one second bitline and the at least one third bitline concurrently with the applying the first bitline voltage to the at least one first bitline. 
     
     
       49. The method of claim 48, wherein, during the second program time, applying the program inhibit voltage to the at least one first bitline concurrently with the applying the second bitline voltage to the at least one second bitline. 
     
     
       50. The method of claim 48, wherein a first programming operation corresponding to the first data value, and at least one of a second programming operation corresponding to the second data value and a third programming operation corresponding to the third data value are completed substantially simultaneously. 
     
     
       51. The method of claim 48, wherein a first programming operation corresponding to the first data value, and at least one of a second programming operation corresponding to the second data value and a third programming operation corresponding to the third data value are completed at a same program loop. 
     
     
       52. The method of claim 47, wherein the second programming pulse is applied to the wordline after the applying the first programming pulse. 
     
     
       53. The method of claim 47, wherein the first wordline verification pulse, the second wordline verification pulse and the third wordline verification pulse are applied to the wordline successively. 
     
     
       54. The method of claim 53, wherein a voltage level of the first wordline verification pulse is lower than a voltage level of the second wordline verification pulse, and
 the voltage level of the second wordline verification pulse is lower than a voltage level of the third wordline verification pulse.