Memory device, manufacturing method and operating method of the same

Abstract

A memory device, a manufacturing method and an operating method of the same are provided. The memory device includes a substrate, stacked structures, a channel element, a dielectric element, a source element, and a bit line. The stacked structures are disposed on the substrate. Each of the stacked structures includes a string selection line, a word line, a ground selection line and an insulating line. The string selection line, the word line and the ground selection line are separated from each other by the insulating line. The channel element is disposed between the stacked structures. The dielectric element is disposed between the channel element and the stacked structure. The source element is disposed between the upper surface of the substrate and the lower surface of the channel element. The bit line is disposed on the upper surface of the channel element.

What is claimed is: 
     
       1. A memory device, comprising:
 a substrate; 
 a plurality of stacked structures disposed on the substrate, wherein each of the stacked structures comprises a string selection line, a word line, a ground selection line and an insulating line lines, the string selection line, the word line and the ground selection line are separated from each other by the insulating line lines; 
 a channel element disposed between the stacked structures; 
 a dielectric element disposed between the channel element and the stacked structure; 
 a source element disposed between an upper surface of a substrate and the lower surface of the channel element; and 
 a bit line disposed on the upper surface of the channel element. 
 
     
     
       2. The memory device according to  claim 1 , wherein the source element and the substrate are separated from each other by the dielectric element, the substrate is used as a bottom gate. 
     
     
       3. The memory device according to  claim 1 , wherein the string selection line, the word line and the ground selection line have a first type conductivity, the source element, the channel element and the bit line have a second type conductivity opposite to the first type conductivity, the channel element has a dopant concentration smaller than dopant concentrations that the source element and the bit line have. 
     
     
       4. The memory device according to  claim 1 , wherein the bit line, the string selection line, the word line and the ground selection line have a first type conductivity, the source element and the channel element have a second type conductivity opposite to the first type conductivity, the channel element has a dopant concentration smaller than a dopant concentration that the source element has. 
     
     
       5. The memory device according to  claim 1 , wherein the bit line has a first type conductivity, the channel element has a second type conductivity opposite to the first type conductivity. 
     
     
       6. The memory device according to  claim 1 , wherein the channel element and the bit line form a PN diode. 
     
     
       7. The memory device according to  claim 1 , wherein the source element comprises a source layer covering the substrate. 
     
     
       8. The memory device according to  claim 1 , wherein the channel element comprises a plurality of channel lines, the source element comprises a plurality of source lines,
 one of the source lines below the channel lines on the same sidewall of the stacked structure is continuously extended; 
 the source lines below the channel lines on the opposite sidewalls of the stacked structure are separated from each other. 
 
     
     
       9. The memory device according to  claim 1 , wherein the channel element comprises a plurality of channel lines, the source element comprises a plurality of source lines, the channel line has a long side perpendicular to a long side that the source line has. 
     
     
       10. A method for manufacturing a memory device, comprising:
 disposing a plurality of stacked structures on a substrate, wherein each of the stacked structures comprises a string selection line, a word line, a ground selection line and an insulating line lines, the string selection line, the word line and the ground selection line are separated from each other by the insulating line lines; 
 disposing a channel element between the stacked structures; 
 disposing a dielectric element between the channel element and the stacked structure; 
 disposing a source element between an upper surface of the substrate and a lower surface of the channel element; and 
 disposing a bit line on the upper surface of the channel element. 
 
     
     
       11. The method for manufacturing the memory device according to  claim 10 , wherein the stacked structures has a space therebetween, the source element comprises a source line, the method for manufacturing the memory device comprises:
 forming a dielectric element on the substrate and the stacked structures exposed by the space; 
 forming a conductive material for filling the space; and 
 removing a portion of the conductive material for forming the source line and the channel element, wherein the source line and the channel element are disposed in the space, the source line and the substrate are separated from each other by the dielectric element. 
 
     
     
       12. The method for manufacturing the memory device according to  claim 11 , wherein the conductive material is extended on the stacked structure, the bit line is formed by a method comprising:
 doping a portion of the conductive material extended on the stacked structure; and 
 removing a portion of the doped conductive material for forming the bit line. 
 
     
     
       13. The method for manufacturing the memory device according to  claim 10 , wherein the source element comprises a source layer covering the substrate, the method for manufacturing the memory device comprises:
 alternately stacking a plurality of sacrificial layers and a plurality of insulating layers; 
 forming a first opening in the alternately-stacked sacrificial layers and insulating layers; 
 forming the channel element by an epitaxial growth on the source layer exposed by the first opening; 
 forming a second opening in the alternately-stacked sacrificial layers and insulating layers; 
 removing the sacrificial layer exposed by the second opening for forming a slit exposing the channel element; 
 forming the dielectric element exposed by the slit; and 
 forming a conductive material filling in the slit for forming the string selection line, the word line and the ground selection line. 
 
     
     
       14. The method for manufacturing the memory device according to  claim 13 , wherein the source layer and the channel element are composed of a single crystal material, and the channel element is formed by an epitaxial growth. 
     
     
       15. The method for manufacturing the memory device according to  claim 13 , wherein the source layer is a single crystal silicon, the insulating line is an oxide, the sacrificial layer is a silicon nitride, the second opening exposes the source layer and the insulating line, the sacrificial layer exposed by the second opening is removed by a method using a hot H3PO4. 
     
     
       16. A method for operating a memory device, comprising:
 providing a memory device comprising: 
 a substrate; 
 a plurality of stacks of horizontal lines of conductive material stacked structures disposed on vertically over the substrate, wherein each of the stacked structures comprises stacks in the plurality of stacks includes horizontal lines configured respectively as a string selection line, a word line, and a ground selection line and an insulating line, the string selection line, the word line and the ground selection line are being separated from each other by the insulating line lines; 
 a channel element comprising a plurality of channel lines, the channel lines are being disposed vertically between the stacked structures stacks and separated from each other; 
 a dielectric element material disposed between the channel lines and sides of the stacked structures stacks; 
 a source element disposed between an upper surface of the substrate and a lower surface of in electrical communication with the channel lines; and 
 a bit line disposed on a upper surface of in electrical communication with the channel element; and lines, wherein the method comprises selecting at least one of the channel lines to be turned on. 
 
     
     
       17. The method for operating the memory device according to  claim 16 , wherein the string selection line, the word line and the ground selection line have a first type conductivity, the source element, the channel element and the bit line have a second type conductivity opposite to the first type conductivity,
 the channel line is turned on by a method comprising:wherein said selecting comprises: 
 applying a first bias voltage to the string selection lines of the stacked structures stacks of horizontal lines on the two opposite sidewalls of the selected channel line. 
 
     
     
       18. The method for operating the memory device according to  claim 17 , further comprising wherein said selecting comprises applying a second bias voltage to the string selection line of the stacked structure stacks on one sidewall of the channel line not selected and to be turned off, wherein the turned off channel line and the turned-on channel line have the common string selection line that the first bias voltage applied to, the first bias voltage is opposite to the second bias voltage. 
     
     
       19. The method for operating the memory device according to  claim 18 , wherein the first type conductivity is P type conductivity, the second type conductivity is N type conductivity, the first bias voltage is a positive bias voltage, and the second bias voltage is a negative bias voltage. 
     
     
       20. The method for operating the memory device according to  claim 17 , further comprising applying a second bias voltage to the string selection lines of the stacked structures stacks on the opposite sidewalls of the channel line not selected and to be turned off. 
     
     
       21. The method for operating the memory device according to  claim 20 , wherein the first bias voltage and the second bias voltage are respectively applied to a portion adjacent to the channel line to be turned on and a portion adjacent to the channel line to be turned off of the single string selection line. 
     
     
       22. The method for operating the memory device according to  claim 16 , further comprising applying a third bias voltage and a fourth bias voltage different from each other to the word lines of the stacked structures stacks on the two opposite sidewalls of the channel line. 
     
     
       23. The method for operating the memory device according to  claim 22 , wherein the third bias voltage is V PGM  or V READ , the fourth bias voltage is zero. 
     
     
       24. The method for operating the memory device according to  claim 16 , wherein the bit line, the string selection line, the word line and the ground selection line have a first type conductivity, the source element and the channel lines have a second type conductivity,
 the selected channel line is turned on by a method comprising: 
 applying a zero voltage or grounding the source element below the selected channel line. 
 
     
     
       25. The method for operating the memory device according to  claim 16 , further comprising floating the second channel line, and applying a fifth bias voltage to the source element below the channel line unselected and to be turned off. 
     
     
       26. The method for operating the memory device according to  claim 25 , wherein the first type conductivity is P type conductivity, the second type conductivity is N type conductivity, the fifth bias voltage is a positive bias voltage. 
     
     
       27. A memory device, comprising:
 a plurality of stacks of horizontal lines of conductive material, each comprising;
 a string selection line, 
 a word line, and 
 a ground selection line, 
   a channel element comprising;
 a first channel line disposed between a first stack and a second stack of the plurality of stacks; and 
 a second channel line disposed between the second stack and a third stack of the plurality of stacked structures; 
   a first charge storing element between and contacting the second channel line and the word line of the first stack;   a second charge storing element between and contacting the second channel line and the word line of the second stack; and   wherein the word line of the first stack and the word line of the second stack are electrically separate in the memory device such that different bias voltages may be applied concurrently to the word line of the first stack and the word line of the second stack to access selectively the first charge storing element or the second charge storage element.   
     
     
       28. The memory device according to claim 27, including a source element contacting the first and second channel lines, and a bit line contacting the first and second channel lines, wherein the string selection lines, the word lines and the ground selection lines have a first type conductivity, and the source element, the first and second channel lines and the bit line have a second type conductivity opposite to the first type conductivity. 
     
     
       29. The memory device according to claim 27, including a source element contacting the first and second channel lines, and a bit line contacting the first and second channel lines, wherein the bit line, the string selection lines, the word lines and the ground selection line have a first type conductivity, and the source element and the first and second channel lines have a second type conductivity opposite to the first type conductivity. 
     
     
       30. The memory device according to claim 27, including a source element contacting the first and second channel lines, and a bit line contacting the first and second channel lines, wherein the bit line has a first type conductivity, and the first and second channel lines have a second type conductivity opposite to the first type conductivity. 
     
     
       31. The memory device according to claim 27, including a source element contacting the first and second channel lines, and a bit line contacting the first and second channel lines, wherein the first channel line and the bit line form a PN diode. 
     
     
       32. The memory device according to claim 27, including a source element in electrical communication with the first and second channel lines, and a bit line in electrical communication with the first and second channel lines. 
     
     
       33. The memory device according to claim 27, including a source element disposed below and contacting the first and second channel lines, and a bit line disposed above and contacting the first and second channel lines. 
     
     
       34. A method for manufacturing a memory device, comprising:
 disposing a plurality of stacks of horizontal lines of conductive material on a substrate, wherein each of the stacks comprises a string selection line, a word line, and a ground selection line;   disposing a channel element between the stacks, the channel element comprising:
 a first channel line disposed between a first and a second stacks of the plurality of stacks; and 
 a second channel line disposed between the second stack and a third stack of the plurality of stacks; 
   disposing a first charge storing element between and contacting the second channel line and the word line of the first stack;   disposing a second charge storing element between and contacting the second channel line and the word line of the second stack;   wherein the word line of the first stack and the word line of the second stack are electrically separate in the memory device such that different bias voltages may be applied concurrently to the word line of the first stack and the word line of the second stack.   
     
     
       35. The method of claim 34, including:
 disposing a source element comprising source lines below and contacting the first and second channel lines; and   disposing a bit line above and contacting the first and second channel lines.   
     
     
       36. A method for operating a memory device comprising:
 a plurality of stacks of horizontal lines of conductive material, each comprising:
 a string selection line; 
 a word line; and 
 a ground selection line; 
 wherein the first channel line is disposed between a first stack and a second stack of the plurality of stacks; and 
 a second channel line is disposed between the second stack and a third stack of the plurality of stacks; 
 a first charge storing element between and contacting the second channel line and the word line of the first stack; 
 a second charge storing element between and contacting the second channel line and the word line of the second stack; and 
   the method comprising:   applying a first bias voltage to the word line of the first stack; and   applying a second bias voltage, different than the first bias voltage, to the word line of the second stack in an operation to selectively read or program data in either of the first or second charge storage elements.   
     
     
       37. The method for operating the memory device according to claim 36, wherein the string selection lines, the word lines and the ground selection lines have a first type conductivity, the source element, the channel element and the bit line have a second type conductivity opposite to the first type conductivity; and
 wherein the first type conductivity is P type conductivity, the second type conductivity is N type conductivity, the first bias voltage is a positive bias voltage, and the second bias voltage is a negative bias voltage.   
     
     
       38. The method for operating the memory device according to claim 36, wherein the first bias voltage is V PGM  or V READ . 
     
     
       39. The method for operating the memory device according to claim 36, wherein the bit lines, the string selection lines, the word lines and the ground selection lines have a first conductivity type, and the source element and the channel lines have a second conductivity type.