Liquid crystal display apparatus having data lines with curved portions and method

Abstract

A liquid crystal display apparatus includes a plurality of data lines each having a plurality of straight line portions and a plurality of curved portions connected to a plurality of the straight line portions; a plurality of gate lines intersecting the data lines; thin film transistors connected to the data lines and the gate lines; and pixel electrodes connected to the thin film transistors. Accordingly, even in a case where driver inversion becomes column inversion, apparent inversion can become dot inversion. As a result, it is possible to eliminate transverse line flicker and to increase a charging rate of pixels. In addition, uniformity of the pixels can be maintained, so that the inversion driving schemes can be applied to a PVA mode. As a result, it is possible to obtain a wide viewing angle and to improve side or lateral visibility.

What is claimed is: 
     
       1. A liquid crystal display apparatus comprising:
 a plurality of data lines, each of the plurality of data lines having a plurality of straight line portions and a plurality of curved portions connected to the plurality of straight line portions;   a plurality of gate lines disposed substantially perpendicular to the plurality of data lines;   a plurality of thin film transistors connected to the plurality of data lines and the plurality of gate lines; and   a plurality of pixel electrodes respectively connected to the plurality of thin film transistors,   wherein the plurality of straight line portions and the plurality of curved portions for each data line of the plurality of data lines are linearly aligned, and   wherein each of the plurality of curved portions comprises:
 a substantially concave surface; and 
 a substantially convex surface opposing the substantially concave surface, 
 wherein a terminal of the substantially concave surface and a terminal of the substantially convex surface both meet a terminal of the straight line portion adjacent to the curved portion, and 
 wherein both the substantially concave surface and the substantially convex surface are disposed on a first side of two extended edges of the straight line portion adjacent to the curved portion, and 
 wherein a remainder of the curved portion is disposed on a second side of the two extended edges of the straight line portion and includes a first linear branch and a second linear branch disposed substantially opposite the first linear branch defining a space therebetween. 
   
     
     
       2. The liquid crystal display apparatus of  claim 1 , wherein channels of the thin film transistors are disposed in extension lines of the straight line portions of the data lines. 
     
     
       3. The liquid crystal display apparatus of  claim 1 , wherein the curved portions constitute source electrodes of the thin film transistors. 
     
     
       4. The liquid crystal display apparatus of  claim 3 , further comprising drain electrodes connected to the pixel electrodes, wherein each of the curved portions surrounds an end of a respective drain electrode. 
     
     
       5. The liquid crystal display apparatus of  claim 4 , wherein the drain electrodes are at least one of located substantially at a same position in each pixel and are substantially symmetrically disposed in a pixel array matrix. 
     
     
       6. The liquid crystal display apparatus of  claim 1 , wherein the curved portions are U-shaped. 
     
     
       7. The liquid crystal display apparatus of  claim 1 , wherein the curved portions have inlets which open in opposite directions every pixel row. 
     
     
       8. The liquid crystal display apparatus of  claim 1 , further comprising shielding electrodes which cover the straight line portions of the data lines and at least partially overlap the curved portions of the data lines. 
     
     
       9. The liquid crystal display apparatus of  claim 1 , wherein the thin film transistors of different pixel rows are connected to the data lines of different sides. 
     
     
       10. The liquid crystal display apparatus of  claim 1 , wherein polarities of data voltages of adjacent data lines are opposite to each other. 
     
     
       11. The liquid crystal display apparatus of  claim 1 , wherein polarities of data voltages of adjacent data lines are the same. 
     
     
       12. The liquid crystal display apparatus of  claim 1 , wherein each of the pixel electrodes has at least one cut portion. 
     
     
       13. The liquid crystal display apparatus of  claim 1 , wherein each of the pixel electrodes includes a first sub-pixel electrode connected to the drain electrode and a second sub-pixel electrode capacitively-coupled with the first sub-pixel electrode. 
     
     
       14. The liquid crystal display apparatus of  claim 13 , wherein a voltage charged in the first sub-pixel electrode is larger than a voltage charged in the second sub-pixel electrode. 
     
     
       15. The liquid crystal display apparatus of  claim 1 , wherein the plurality of thin film transistors are connected to opposite sides of the plurality of data lines alternately every pixel row, and
 openings of a plurality of pixels associated with the plurality of pixel electrodes have substantially a same shape.   
     
     
       16. A liquid crystal display apparatus comprising:
 a plurality of data lines each having a plurality of first straight line portions, a plurality of second straight line portions alternately linearly disposed with the first straight line portions, and   a plurality of first and second curved portions alternately connected between the first and second straight line portions;   a plurality of pairs of first and second gate lines disposed substantially perpendicular to the plurality of data lines;   a plurality of pairs of first and second thin film transistors connected to the plurality of pairs of first and second gate lines, respectively, and the plurality of data lines; and   a plurality of pixel electrodes connected to the plurality of first and second thin film transistors, each of the plurality of pixel electrodes comprising first and second sub-pixel electrodes respectively connected to a pair of first and second thin film transistors of the plurality of pairs of first and second thin film transistors,   wherein the first and second thin film transistors comprise first and second drain electrodes connected to the first and second sub-pixel electrodes, respectively, the first and second drain electrodes each comprising a first end portion surrounded by one of the plurality of first and second curved portions, and a second end portion extending from the first end portion in a transverse direction substantially parallel to the first and second gate lines,   wherein each of the first and second curved portions comprises:
 a substantially concave surface; and 
 a substantially convex surface opposing the substantially concave surface, 
 wherein a terminal of the concave surface and a terminal of the convex surface of each of the first and second curved portions both meet a terminal of one of the first and second straight line portions adjacent to each of the first and second curved portions, and 
 wherein both of the substantially concave surface and the substantially convex surface of at least one of the first curved portion and the second curved portion are disposed on a same side with respect to two extended edges of the first and second straight line portions adjacent to the at least one of the first and second curved portions. 
   
     
     
       17. The liquid crystal display apparatus of  claim 16 , wherein magnitudes of first and second data voltages applied to the first and second sub-pixel electrodes, respectively, are different from each other and are obtained from single image information. 
     
     
       18. The liquid crystal display apparatus of  claim 16 , wherein the first and second straight line portions of each data line and the respective first and second curved portions are disposed substantially in the same line. 
     
     
       19. The liquid crystal display apparatus of  claim 18 , wherein channels of the first and second thin film transistors are disposed in extension lines of the first and second straight line portions of the data lines. 
     
     
       20. The liquid crystal display apparatus of  claim 18 , wherein the first and second drain electrodes are at least one of located substantially at a same position in respective pixels and are substantially symmetrically disposed in a pixel array matrix. 
     
     
       21. The liquid crystal display apparatus of  claim 18 , wherein the first and second thin film transistors are connected to the data lines of different sides alternately in every pixel row. 
     
     
       22. The liquid crystal display apparatus of  claim 21 , wherein polarities of data voltages of adjacent data lines are opposite to each other. 
     
     
       23. The liquid crystal display apparatus of  claim 21 , wherein polarities of data voltages of one of adjacent data lines to a data line therebetween are the same. 
     
     
       24. A liquid crystal display apparatus comprising:
 a plurality of pixels arrayed in a matrix and each of the plurality of pixels having pixel electrodes;   a plurality of gate lines connected to the plurality of pixels and each of the plurality of gate lines having a plurality of gate electrodes;   a plurality of data lines disposed substantially perpendicular to the plurality of gate lines and having a plurality of source electrodes; and   a plurality of drain electrodes facing respective source electrodes of the plurality of source electrodes and connected to the respective pixel electrodes,   wherein each of the plurality of drain electrodes comprises:
 a first end portion disposed substantially opposite a respective source electrode of the plurality of source electrodes; 
 a second end portion extending from the first end portion substantially parallel to the plurality of gate lines the second end portion being directly connected with the first end portion; 
 a first portion extending from a connection point between the first end portion and the second end portion in a direction substantially parallel to the plurality of data lines, the first portion extending away from both the first end portion and the second end portion, the first portion comprising an end disposed at the connection point between the first end portion and the second end portion; and 
 an enlarged portion connected to another end of the first portion and connected to the respective pixel electrode of the plurality of pixel electrodes. 
   
     
     
       25. The liquid crystal display apparatus of  claim 24 , wherein the gate lines include dummy gate electrodes having substantially the same shape as the gate electrodes. 
     
     
       26. The liquid crystal display apparatus of  claim 24 , further comprising dummy drain electrodes which are at least one of located substantially at same positions as the drain electrodes and are substantially symmetrically disposed in a pixel array matrix. 
     
     
       27. The liquid crystal display apparatus of  claim 24 , wherein two pixels are disposed between two adjacent data lines. 
     
     
       28. The liquid crystal display apparatus of  claim 24 , wherein the switching devices and the data lines are substantially linearly aligned relative to each other. 
     
     
       29. The liquid crystal display apparatus of  claim 24 , wherein adjacent source electrodes are oriented in different directions with respect to the data lines. 
     
     
       30. The liquid crystal display apparatus of  claim 24 , wherein switching devices having the gate, source, and drain electrodes and residing in adjacent pixels are disposed at different locations within the adjacent pixels with respect to the pixel electrodes of the adjacent pixels, and
 wherein openings of the plurality of pixels have substantially a same shape.   
     
     
       31. A thin film transistor panel comprising:
 thin film transistors having gate electrodes, source electrodes and drain electrodes, respectively;   a gate line connected to the gate electrodes of the thin film transistors;   dummy gate electrodes connected to and extended from the gate line in a same direction as the gate electrodes, the dummy gate electrodes having the same shape and size as the gate electrodes, and each dummy gate electrode being disposed between adjacent gate electrodes.   
     
     
       32. The thin film transistor panel of claim 31, wherein the gate electrodes are separated from each other by a first pitch, and the dummy gate electrodes are separated from each other by a second pitch which is equal to the first pitch. 
     
     
       33. The thin film transistor panel of claim 31, further comprising:
 pixel electrodes connected to the drain electrodes of the thin film transistors; and   dummy drain electrodes connected to the pixel electrodes, the dummy drain electrodes having the same shape with each other.   
     
     
       34. The thin film transistor panel of claim 33, further comprising:
 a protective film disposed between the thin film transistors and the pixel electrode, and having contact holes exposing the dummy drain electrodes, the pixel electrodes being connected to the dummy drain electrodes through the contact holes.   
     
     
       35. The thin film transistor panel of claim 33, further comprising a storage electrode line having branches overlapping the pixel electrodes. 
     
     
       36. A thin film transistor panel comprising:
 thin film transistors arranged in a matrix, the thin film transistors having gate electrodes, source electrodes, and drain electrodes;   a first gate line connected to the gate electrodes of the thin film transistors disposed in a first row of the matrix;   a second gate line connected to the gate electrodes of the thin film transistors disposed in a second row of the matrix;   first dummy gate electrodes connected to and extended from the first gate lines in a same direction as the gate electrodes connected to the first gate line, the first dummy gate electrodes having the same shape and size as the gate electrodes connected to the first gate line, and each first dummy gate electrode being disposed between adjacent gate electrodes connected to the first gate line; and   second dummy gate electrodes connected to and extended from the second gate lines in a same direction as the gate electrodes connected to the second gate line, the second dummy gate electrodes having the same shape and size as the gate electrodes connected to the second gate line, and each second dummy gate electrode being disposed between adjacent gate electrodes connected to the second gate line.   
     
     
       37. The thin film transistor panel of claim 36, wherein the gate electrodes connected to the first gate line are separated from each other by a first pitch, and the first dummy gate electrodes are separated from each other by a second pitch which is equal to the first pitch. 
     
     
       38. The thin film transistor panel of claim 37, wherein the gate electrodes connected to the second gate line are separated from each other by the first pitch, and the second dummy gate electrodes are separated from each other by the second pitch. 
     
     
       39. The thin film transistor panel of claim 36, further comprising:
 a first pixel electrode connected to one of the thin film transistors disposed in the first row;   a second pixel electrode connected to one of the thin film transistors disposed in the second row, the second pixel electrode being longitudinally adjacent to the first pixel electrode;   a first dummy drain electrode connected to the first pixel electrode; and   a second dummy drain electrode connected to the second pixel electrode,   wherein a location of the first dummy drain electrode with respect to the first pixel electrode is different from a location of the second dummy drain electrode with respect to the second pixel electrode.   
     
     
       40. The thin film transistor panel of claim 39, wherein the second dummy drain electrode has the same shape as the first dummy drain electrode. 
     
     
       41. The thin film transistor panel of claim 39, further comprising:
 a protective film disposed between the thin film transistors and the pixel electrodes, and having contact holes exposing the dummy drain electrodes, the pixel electrodes being connected to the dummy drain electrodes through the contact holes.   
     
     
       42. The thin film transistor panel of claim 39, further comprising a storage electrode line having branches overlapping the pixel electrodes.