Isolation region fabrication for replacement gate processing

Abstract

A semiconductor structure includes a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a bottom silicon layer, a buried oxide (BOX) layer, and a top silicon layer; a plurality of active devices formed on the top silicon layer; and an isolation region located between two of the active devices, wherein at least two of the plurality of active devices are electrically isolated from each other by the isolation region, and wherein the isolation region extends through the top silicon layer to the BOX layer.

The invention claimed is: 
     
       1. A semiconductor structure, comprising:
 a silicon-on-insulator (SOI) substrate, the SOI substrate comprising a bottom silicon layer, a buried oxide (BOX) layer, and a top silicon layer; 
 a plurality of active devices formed on the top silicon layer; and 
 an isolation region located between two of the plurality of active devices, wherein at least the two of the plurality of active devices are electrically isolated from each other by the isolation region, wherein the isolation region extends through the top silicon layer to the BOX layer, wherein the isolation region further extends between a pair of spacers that are located on the top silicon layer on either side of the isolation region to provide an inactive device between the two of the plurality of active devices, and wherein the isolation region further extends through an interlevel dielectric (ILD) layer that is located over the pair of spacers of the inactive device. 
 
     
     
       2. The semiconductor structure of  claim 1 , further comprising a hardmask layer located over the isolation region. 
     
     
       3. The semiconductor structure of  claim 2 , wherein the hardmask layer comprises silicon nitride. 
     
     
       4. A semiconductor structure, comprising:
 a substrate;   a plurality of active devices on the substrate; and   an isolation region located between two of the plurality of active devices, wherein the two of the plurality of active devices are electrically isolated from each other by the isolation region, wherein the isolation region extends into the substrate, wherein the isolation region further extends between a pair of spacers that are located on the substrate on either side of the isolation region to provide an inactive device between the two of the plurality of active devices, and wherein the isolation region further extends through an interlevel dielectric (ILD) layer that is located over the pair of spacers of the inactive device.   
     
     
       5. The semiconductor structure of claim 4 further comprising:
 a plurality of pairs of gate spacers, wherein each of the plurality of active devices comprises a respective gate electrode and a respective one of the plurality of pairs of gate spacers on opposing sides of the respective gate electrode.   
     
     
       6. The semiconductor structure of claim 5 wherein a distance between each of the plurality of pairs of gate spacers through the respective gate electrode is about equal to a distance between the pair of spacers that are located on the substrate on either side of the isolation region. 
     
     
       7. The semiconductor structure of claim 14 wherein the pair of spacers absent from between the isolation region and the substrate. 
     
     
       8. The semiconductor structure of claim 4 wherein the ILD layer and isolation region are separate structures. 
     
     
       9. The semiconductor structure of claim 4 wherein the pair of spacers comprise replacement gate spacers. 
     
     
       10. The semiconductor structure of claim 4 wherein the ILD layer surrounds the isolation region. 
     
     
       11. The semiconductor structure of claim 4 wherein the plurality of active devices comprise finFET active devices. 
     
     
       12. The semiconductor structure of claim 11 wherein the finFET active devices comprise respective gate electrodes surrounded by respective gate spacers. 
     
     
       13. The semiconductor structure of claim 12 wherein an uppermost surface of the isolation region is above a lowest portion of a gate electrode included in the plurality of active devices. 
     
     
       14. The semiconductor structure of claim 4 wherein the isolation region penetrates the pair of spacers into the substrate. 
     
     
       15. A semiconductor structure, comprising:
 a substrate;   a plurality of active fins extending parallel to one another in a first direction on the substrate, wherein at least one of the plurality of active fins is included in a plurality of respective finFET active devices spaced apart in the first direction on the substrate;   a plurality of adjacent insulation regions in the substrate, respective ones of which are located between adjacent ones of the plurality of fins; and   an isolation region located between two of the plurality of respective finFET active devices spaced apart in the first direction, wherein the two of the plurality of respective finFET active devices are electrically isolated from each other by the isolation region, wherein the isolation region extends into the substrate, wherein the isolation region further extends between a pair of spacers that are located on the substrate on first and second sides the isolation region to provide an inactive finFET device between the two of the plurality of respective finFET active devices, and wherein the isolation region further extends through a interlevel dielectric (ILD) layer that is located over the pair of spacers of the finFET inactive device.   
     
     
       16. The semiconductor structure of claim 15 wherein the isolation region penetrates the pair of spacers into the substrate. 
     
     
       17. The semiconductor structure of claim 15 wherein the ILD layer surrounds the isolation region. 
     
     
       18. A semiconductor structure, comprising:
 a substrate;   a plurality of fins extending parallel to one another in a first direction on the substrate and spaced apart on the substrate in a second direction, at least one of the plurality of fins being segmented by an isolation region into a plurality of respective finFET active devices spaced apart in the first direction on the substrate; and   a plurality of adjacent insulation regions in the substrate, respective ones of which are located between adjacent ones of the plurality of fins,   wherein the isolation region is located between two of the plurality of respective finFET active devices spaced apart in the first direction, wherein the two of the plurality of respective finFET active devices are electrically isolated from each other by the isolation region, wherein the isolation region extends into the substrate, wherein the isolation region further extends between a pair of spacers that are located on the substrate on first and second sides of the isolation region to provide an finFET inactive device between the two of the plurality of respective finFET active devices, and wherein the isolation region further extending through an interlevel dielectric (ILD) layer that is located over the pair of spacers of the finFET inactive device.   
     
     
       19. The semiconductor structure of claim 18 wherein the ILD layer surrounds the isolation region. 
     
     
       20. The semiconductor structure of claim 18 wherein the isolation region penetrates the pair of spacers into the substrate. 
     
     
       21. A semiconductor structure, comprising:
 a substrate;   a first active device on the substrate, the first active device having a first gate electrode and first spacers on opposing sides of the first gate electrode;   a second active device on the substrate, the second active device having a second gate electrode and second spacers on opposing sides of the second gate electrode; and   an isolation region located on the substrate between the first and second active devices, wherein the first and second active devices are electrically isolated from each other by the isolation region, wherein the isolation region extends into the substrate, wherein the isolation region further extends between third spacers that are located on the substrate on either side of the isolation region to provide an inactive device between the first and second active devices, and wherein the isolation region further extends through an interlevel dielectric (ILD) layer that is located over the third spacers.