Isolation region fabrication for replacement gate processing

Abstract

A method for isolation region fabrication for replacement gate integrated circuit (IC) processing includes forming a plurality of dummy gates on a substrate; forming a block mask over the plurality of dummy gates, such that the block mask selectively exposes a dummy gate of the plurality of dummy gates; removing the exposed dummy gate to form an isolation region recess corresponding to the removed dummy gate; filling the isolation region recess with an insulating material to form an isolation region; removing the block mask to expose a remaining plurality of dummy gates; and performing replacement gate processing on the remaining plurality of dummy gates to form a plurality of active devices, wherein at least two of the plurality of active devices are electrically isolated from each other by the isolation region.

The invention claimed is: 
     
       1. A method for isolation region fabrication for replacement gate integrated circuit (IC) processing, the method comprising:
 forming a plurality of dummy gates on a substrate; 
 forming a block mask over the plurality of dummy gates, such that the block mask selectively exposes a dummy gate of the plurality of dummy gates; 
 removing the exposed dummy gate to form an isolation region recess corresponding to the removed dummy gate; 
 filling the isolation region recess with an insulating material to form an isolation region; 
 removing the block mask to expose a remaining plurality of dummy gates; and 
 performing replacement gate processing on the remaining plurality of dummy gates to form a plurality of active devices, wherein at least two of the plurality of active devices are electrically isolated from each other by the isolation region. 
 
     
     
       2. The method of  claim 1 , wherein the substrate comprises a silicon-on-insulator substrate comprising a bottom silicon layer, a buried oxide (BOX) layer located on the bottom silicon layer, and a top silicon layer located on the BOX layer, wherein the plurality of dummy gates are formed on the top silicon layer, and wherein the isolation region recess extends through the top silicon layer down to the BOX layer. 
     
     
       3. The method of  claim 1 , wherein the insulating material comprises one of silicon dioxide and silicon nitride. 
     
     
       4. The method of  claim 1 , wherein removing the exposed dummy gate to form the isolation region recess comprises a sequential multilevel etch. 
     
     
       5. The method of  claim 4 , wherein the sequential multilevel etch comprises:
 etching the exposed dummy gate using a first etch; 
 etching a gate dielectric layer corresponding to the exposed dummy gate using a second etch; and 
 etching a top silicon layer of the substrate down to a buried oxide (BOX) layer of the substrate using a third etch. 
 
     
     
       6. The method of  claim 5 , wherein the exposed dummy gate comprises polysilicon, and the first etch comprises a bromine-based dry etch. 
     
     
       7. The method of  claim 5 , wherein the second etch comprises a hydrofluoric etch. 
     
     
       8. The method of  claim 5 , wherein the gate dielectric layer comprises a bottom dielectric layer located on the substrate, and a top metal layer located on the bottom dielectric layer, and wherein the second etch comprises a two-stage etch. 
     
     
       9. The method of  claim 5 , wherein the third etch comprises a bromine-based dry etch. 
     
     
       10. The method of  claim 1 , further comprising forming a hardmask layer over the isolation region before performing the replacement gate processing on the remaining plurality of dummy gates to form the plurality of active devices. 
     
     
       11. The method of  claim 10 , further comprising removing the hardmask layer after formation of the plurality of active devices. 
     
     
       12. The method of  claim 10 , wherein the hardmask layer comprises silicon nitride. 
     
     
       13. The method of  claim 1 , wherein the block mask comprises photoresist. 
     
     
       14. The method of  claim 1 , wherein the isolation region extends between a pair of spacers that are located on the substrate on either side of the isolation region, and through an interlevel dielectric (ILD) layer that is located over the pair of spacers. 
     
     
       15. A method of manufacturing a semiconductor device, the method comprising:
 forming a plurality of dummy gates on a substrate;   forming an interlevel dielectric layer over the substrate including the plurality of dummy gates;   forming a block mask over the plurality of dummy gates and over the interlevel dielectric layer, such that the block mask selectively exposes a dummy gate of the plurality of dummy gates;   removing the exposed dummy gate to form an isolation region recess corresponding to the removed dummy gate;   filling the isolation region recess with an insulating material to form an isolation region;   removing the block mask to expose a remaining plurality of dummy gates; and   performing replacement gate processing on the remaining plurality of dummy gates to form a plurality of active devices, wherein at least two of the plurality of active devices are electrically isolated from each other by the isolation region.   
     
     
       16. The method of claim 15, further comprising:
 planarizing the interlevel dielectric layer to expose top surfaces of the plurality of dummy gates.   
     
     
       17. The method of claim 15, wherein the isolation region extends through the interlevel dielectric layer. 
     
     
       18. The method of claim 15, wherein forming the block mask comprises forming the block mask to expose a portion of the interlevel dielectric layer, and
 wherein removing the exposed dummy gate comprises removing the exposed dummy gate using the block mask and the exposed portion of the interlevel dielectric layer as etching masks.   
     
     
       19. The method of claim 15 wherein the substrate includes a fin for a finFET. 
     
     
       20. The method of claim 15 further comprising:
 forming spacers on opposing side walls of the plurality of dummy gates beneath the interlevel dielectric layer.   
     
     
       21. The method of claim 20 wherein forming the block mask comprises forming the block mask so that the block mask selectively exposes the dummy gate of the plurality of dummy gates and a pair of the spacers thereon. 
     
     
       22. The method of claim 21 wherein filling the isolation region recess comprises forming the isolation region to extend through the pair of spacers and the interlevel dielectric layer. 
     
     
       23. The method of claim 15 further comprising:
 forming spacers on opposing side walls of the plurality of dummy gates.   
     
     
       24. The method of claim 15 wherein after performing the replacement gate processing a top surface of the interlevel dielectric layer is coplanar with top surfaces of the plurality of active devices. 
     
     
       25. A method for isolation region fabrication for replacement gate integrated circuit (IC) processing, the method comprising:
 forming a plurality of dummy gates on a substrate;   forming spacers on opposing side walls of the plurality of dummy gates;   forming a block mask over the plurality of dummy gates, such that the block mask selectively exposes a dummy gate of the plurality of dummy gates, the exposed dummy gate having a pair of the spacers thereon;   removing the exposed dummy gate to form an isolation region recess corresponding to the removed dummy gate;   filling the isolation region recess with an insulating material to form an isolation region extending between the pair of spacers;   removing the block mask to expose remaining ones of the plurality of dummy gates; and   performing replacement gate processing on the remaining ones of the plurality of dummy gates to form a plurality of active devices, wherein at least two of the plurality of active devices are electrically isolated from each other by the isolation region.   
     
     
       26. The method of claim 25, wherein the substrate includes a fin for a finFET. 
     
     
       27. The method of claim 25, further comprising:
 prior to forming the block mask, forming an interlevel dielectric layer over the substrate including the plurality of dummy gates; and   planarizing the interlevel dielectric layer to expose top surfaces of the dummy gates.   
     
     
       28. The method of claim 27, wherein the isolation region extends through the pair of spacers and the interlevel dielectric layer. 
     
     
       29. The method of claim 27, wherein forming the block mask comprises forming the block mask to expose a portion of the interlevel dielectric layer, and
 wherein removing the exposed dummy gate comprises removing the exposed dummy gate using the block mask and the exposed portion of the interlevel dielectric layer as etching masks.   
     
     
       30. The method of claim 25 further comprising:
 prior to forming the block mask, forming an interlevel dielectric layer over the substrate including the plurality of dummy gates; and   wherein after performing the replacement gate processing a top surface of the interlevel dielectric layer is coplanar with top surfaces of the plurality of active devices.   
     
     
       31. A method of manufacturing a semiconductor device, the method comprising:
 forming a plurality of dummy gates on a substrate;   forming a mask over the plurality of dummy gates, such that the mask selectively exposes a dummy gate of the plurality of dummy gates;   removing the exposed dummy gate to form an isolation region recess corresponding to the removed dummy gate;   depositing an insulating material in the isolation region recess to form an isolation region;   removing the mask to expose a remaining plurality of dummy gates; and   performing replacement gate processing on the remaining plurality of dummy gates to form a plurality of active devices, wherein at least two of the plurality of active devices are electrically isolated from each other by the isolation region.   
     
     
       32. A method of manufacturing a semiconductor device, the method comprising:
 forming a plurality of dummy gates on a substrate;   removing a selected dummy gate from the plurality of dummy gates to form an isolation region recess corresponding to the selected dummy gate;   depositing an insulating material in the isolation region recess to form an isolation region;   exposing remaining ones of the plurality of dummy gates; and   performing replacement gate processing on the remaining ones of the plurality of dummy gates to form a plurality of active devices, wherein at least two of the plurality of active devices are electrically isolated from each other by the isolation region.