Charge pump circuit

Abstract

A charge pump circuit includes a first plurality of capacitors, and a first precharge circuit. The first plurality of capacitors are connected in parallel to each other. The first plurality of capacitors receive clock signals to perform sequentially pumping operations which generate a first higher voltage from a power voltage supplied. The first precharge circuit precharges a predetermined number of capacitors in the first plurality of capacitors at the power voltage. The predetermined number is greater than one.

What is claimed is: 
     
       1. A charge pump circuit comprising:
 a first charge pump circuit comprising:  a first plurality of capacitors that are connected in parallel to each other, the first plurality of capacitors receiving clock signals to perform sequentially pumping operations which generate a first higher voltage from a power voltage supplied at a first output node; and    a first precharge circuit that precharges a first predetermined number of capacitors in the first plurality of capacitors at the power voltage;   
 a second charge pump circuit comprising:  a second plurality of capacitors that are connected in parallel to each other, the second plurality of capacitors receiving clock signals to perform sequentially pumping operations which generate a second higher voltage from the power voltage at a second output node; and    a second precharge circuit that precharges a second predetermined number of capacitors in the second plurality of capacitors at the power voltage; and   
 a series connection path that connects in series between a the first output node of the first precharge circuit and a the second output node of the second precharge circuit, 
 wherein when the first output node and the second output node are connected in series via the series connection path, a final capacitor of the first plurality of capacitors is connected in the series connection path between the first output node and the second output node,  
 wherein the first predetermined number is greater than one, and 
 wherein the second predetermined number is greater than one. 
 
     
     
       2. The charge pump circuit according to  claim 1 , wherein the first precharge circuit comprises:
 a first precharge path that precharges a first capacitor on a first stage at the power voltage, the first capacitor being included in the first plurality of capacitors which are each provided on different stages, the first stage being included in the different stages, the first capacitor being subjected to a first boosting, the first boosting being the first one of boostings for all capacitors included in the first plurality of capacitors; and 
 a second precharge path that precharges a second capacitor on a follower stage at the power voltage, the follower stage being a second or later stage, 
 
       wherein the second precharge circuit comprises:
 a third precharge path that precharges a third capacitor on a third stage at the power voltage, the third capacitor being included in the second plurality of capacitors which are each provided on different stages, the third stage being included in the different stages, the third capacitor being subjected to a first boosting, the first boosting being the first one of boostings for all capacitors included in the second plurality of capacitors; and 
 a fourth precharge path that precharges a fourth capacitor on a second follower stage at the power voltage, the second follower stage being a second or later stage. 
 
     
     
       3. The charge pump circuit according to  claim 1 , wherein the first precharge circuit comprises:
 a first precharge path that precharges a first capacitor on a first stage at the power voltage, the first capacitor being included in the first plurality of capacitors which are each provided on different stages, the first stage being included in the different stages, the first capacitor being subjected to a first boosting, the first boosting being the first one of boostings for all capacitors included in the first plurality of capacitors; and 
 a first later precharge path that sequentially precharges other capacitors than the first capacitors capacitor, the other capacitors being provided on other stages that sequentially follow to the first stage, 
 wherein the second precharge circuit comprises: 
 a third precharge path that precharges a third capacitor on a third stage at the power voltage, the third capacitor being included in the second plurality of capacitors which are each provided on different stages, the third stage being included in the different stages, the third capacitor being subjected to a first boosting, the first boosting being first one of boostings for all capacitors included in the second plurality of capacitors; and 
 a second later precharge path that sequentially precharges other capacitors than the third capacitors capacitor, the other capacitors being provided on other stages that sequentially follow to the third capacitor. 
 
     
     
       4. The charge pump circuit according to  claim 2 , wherein the first precharge path comprises:
 a first node coupled to the first capacitor; and 
 a first switch between the first node and a power supply that supplies the power voltage, 
 wherein the second precharge path comprises: 
 a second node coupled to the second capacitor; and 
 a second switch between the second node and the power supply, 
 wherein the third precharge path comprises: 
 a third node coupled to the third capacitor; and 
 a third switch between the third node and the power supply, and 
 wherein the fourth precharge path comprises: 
 a fourth node coupled to the fourth capacitor; and 
 a fourth switch between the fourth node and the power supply. 
 
     
     
       5. The charge pump circuit according to  claim 2 , further comprising:
 a clock generator that generates first and second clocks, the clock generator sequentially supplying the first and second clocks to the first and second capacitors respectively, and the clock generator sequentially supplying the first and second clocks to the third and fourth capacitors respectively. 
 
     
     
       6. A charge pump circuit comprising:
 an output terminal;  
 a first charge pump circuit that comprises: a first plurality of capacitors that are connected in parallel to each other, the first plurality of capacitors receiving one or more clock signals to perform sequentially pumping operations which generate a first higher voltage from a power voltage supplied; 
 a second charge pump circuit that comprises: a second plurality of capacitors that are connected in parallel to each other, the second plurality of capacitors receiving one or more clock signals to perform sequentially pumping operations which generate a second higher voltage from the power voltage; and 
 a third charge pump circuit comprising a switch that, when activated, connects in series a first final stage capacitor on the a final stage of the first plurality of capacitors to a second final stage capacitor on the a final stage of the second plurality of capacitors, 
 wherein the final stage capacitor of the second plurality of capacitors is not connected to the output terminal of the charge pump circuit when the switch is inactivated,  
 wherein at least one of the first and second charge pump circuits comprises a precharge circuit that precharges a predetermined number of capacitors at the power voltage, the predetermined number of capacitors are included in the at least one of the first and second charge pump circuits, and  
 wherein the predetermined number is greater than one. 
 
     
     
       7. The charge pump circuit according to  claim 6 , wherein the precharge circuit comprises:
 a first precharge path that precharges a first capacitor on the first stage of the capacitors at the power voltage; and 
 a second precharge path that precharges a second capacitor on a follower stage at the power voltage, the follower stage being a second or later stage. 
 
     
     
       8. The charge pump circuit according to  claim 7 , further comprising:
 a clock generator that generates first and second clocks, the clock generator sequentially supplying the first and second clocks to the first and second capacitors respectively. 
 
     
     
       9. A charge pump circuit comprising:
 a first switch connected between a first power line and a first node; 
 a first capacitor connected between the first node and a first clock supply node; 
 a second switch connected between the first node and a second node; 
 a third switch connected between the first power line and the second node; 
 a second capacitor connected between the second node and a second clock supply node; 
 a fourth switch connected between the second node and a third node; 
 a series circuit that comprises a fifth switch and a third capacitor which are connected in series between the second capacitor and the second clock supply node; 
 a sixth switch connected between a first connecting node and a second power line, the first connecting node being between the second capacitor and the series circuit; 
 a seventh switch connected between the first power line and a fourth node; 
 a fourth capacitor connected between the fourth node and the first clock supply node; 
 an eighth switch connected between the fourth node and a second connecting node, the second connecting node being between the fifth switch and the third capacitor; and 
 a ninth switch connected between the first power line and the second connecting node. 
 
     
     
       10. The charge pump circuit according to  claim 9 , further comprising:
 a clock generator that generates first and second clocks, the clock generator sequentially supplying the first and second clocks to the first and second clock supply nodes respectively. 
 
     
     
       11. The charge pump circuit according to  claim 10 , wherein
 in pre-charging the first and second capacitors with a voltage of the first power line, the first and third switches are in electrically conductive state, and the second and fourth switches are in electrically non-conductive state, and the clock generator sets the first and second clock signals at a first voltage level which does not rise the voltages across each capacitor of the first to fourth capacitors, each capacitor being supplied with the first or second clock signal; 
 in pumping from the first capacitor to the second capacitor, the first, third and fourth switches are in electrically non-conductive state, the second switch is in electrically conductive state, and the clock generator sets the first clock signal at a second voltage level which rises the voltages across each capacitor of the first to fourth capacitors, each capacitor being supplied with the first or second clock signal, and the clock generator sets the second clock signal at the first voltage level; and 
 in discharging from the second capacitor, the first and fourth switches are in electrically conductive state, the second and third switches are in electrically non-conductive state, and the clock generator sets the first clock signal at the first voltage level, and the clock generator sets the second clock signal at the second voltage level. 
 
     
     
       12. The charge pump circuit according to  claim 10 , wherein
 in pre-charging the first, second, third and fourth capacitors with a voltage of the first power line, the first, third, sixth, seventh and ninth switches are in electrically conductive state, and the second, fourth, fifth and eighth switches are in electrically non-conductive state, and the clock generator sets the first and second clock signals at a first voltage level which does not rise the voltages across each capacitor of the first to fourth capacitors, each capacitor being supplied with the first or second clock signal; 
 in pumping from the first capacitor to the second capacitor and also pumping from the fourth capacitor to the second capacitor, the first, third, fourth, fifth, seventh and ninth switches are in electrically non-conductive state, the second, sixth and eighth switches are in electrically conductive state, and the clock generator sets the first clock signal at a second voltage level which rises the voltages across each capacitor of the first to fourth capacitors, each capacitor being supplied with the first or second clock signal, and the clock generator sets the second clock signal at the first voltage level; and 
 in discharging from the second capacitor, the first, fourth, fifth and seventh switches are in electrically conductive state, the second, third, sixth, eighth and ninth switches are in electrically non-conductive state, and the clock generator sets the first clock signal at the first voltage level, and the clock generator sets the second clock signal at the second voltage level. 
 
     
     
       13. A charge pump circuit comprising:
 a first charge pump circuit comprising a first plurality of capacitors that are precharged to a power supply voltage, the first plurality of capacitors receiving one or more clock signals to perform sequentially pumping operations which generate a first higher voltage from the power supply voltage at an output node in a final stage of the first charge pump circuit that includes a final stage capacitor having a first terminal connected to the output node in the final stage of the first charge pump circuit;   a second charge pump circuit comprising a second plurality of capacitors that are precharged to the power supply voltage, the second plurality of capacitors receiving one or more clock signals to perform sequentially pumping operations which generate a second higher voltage from the power supply voltage at an output node in a final stage of the second charge pump circuit that includes a final stage capacitor having a first terminal connected to the output node in the final stage of the second charge pump circuit; and   a third charge pump circuit that connects in series a second terminal of the final stage capacitor of the first charge pump to the output node in the final stage of the second charge pump circuit.    
     
     
       14. The charge pump circuit of claim 13, wherein each of the first charge pump circuit and the second charge pump circuit further comprise a first stage capacitor precharged to the power supply voltage through a first switch, a second stage capacitor precharged to the power supply voltage through a second switch, and a third switch connecting the first stage capacitor to the second stage capacitor.  
     
     
       15. The charge pump circuit of claim 14, wherein the second stage capacitor of each of the first charge pump circuit and the second charge pump circuit is the final stage capacitor of respective first and second charge pump circuits.  
     
     
       16. The charge pump circuit of claim 14, wherein the first, second, and third switches are transistors.  
     
     
       17. The charge pump circuit of claim 16, wherein the transistors are n-channel transistors.  
     
     
       18. The charge pump circuit of claim 13, wherein the final stage capacitor on the final stage of the first plurality of capacitors and the final stage capacitor on the final stage of the second plurality of capacitors are connected in series through a first transistor.  
     
     
       19. The charge pump circuit of claim 18, wherein the first transistor is a p-channel transistor.  
     
     
       20. The charge pump circuit of claim 18, wherein the final stage capacitor on the final stage of the first plurality of capacitors is connected to an output terminal through a second transistor.  
     
     
       21. The charge pump circuit of claim 20, wherein the second transistor is an n-channel transistor.  
     
     
       22. The charge pump circuit of claim 1, wherein, when connected in the series connection path, the final capacitor of the first plurality of capacitors has a first terminal connected to the first output node and a second terminal connected to the second output node.  
     
     
       23. The charge pump circuit of claim 6, wherein the final stage capacitor of the first plurality of capacitors is connectable to the output terminal of the charge pump circuit regardless of whether the switch is activated or inactivated.