Semiconductor device and method for driving the same

Abstract

A semiconductor device includes a semiconductor layer stack 13 formed on a substrate 11 and having a channel region, a first electrode 16 A and a second electrode 16 B formed spaced apart from each other on the semiconductor layer stack 13, a first gate electrode 18 A formed between the first electrode 16 A and the second electrode 16 B, and a second gate electrode 18 B formed between the first gate electrode 18 A and the second electrode 16 B. A first control layer 19 A having a p-type conductivity is formed between the semiconductor layer stack 13 and the first gate electrode 18 A.

The invention claimed is: 
     
       1. A semiconductor device, comprising:
 a semiconductor layer stack of a nitride semiconductor or a silicon carbide semiconductor formed on a substrate and having a channel region; 
 a first electrode and a second electrode formed spaced apart from each other on the semiconductor layer stack; and 
 a first gate electrode formed between the first electrode and the second electrode, and a second gate electrode formed between the first gate electrode and the second electrode, wherein: 
 a potential greater than a threshold voltage of the first gate electrode with reference to a potential of the first electrode is applied to the first gate electrode and a potential less than or equal to a threshold voltage of the second gate electrode with reference to a potential of the second electrode is applied to the second gate electrode, whereby the semiconductor device is brought to a reverse-blocking state in which a current flows from the second electrode to the first electrode but not from the first electrode to the second electrode; and 
 a potential less than or equal to the threshold voltage of the first gate electrode with reference to the potential of the first electrode is applied to the first gate electrode and a potential less than or equal to the threshold voltage of the second gate electrode with reference to the potential of the second electrode is applied to the second gate electrode, whereby the semiconductor device is brought to a non-conductive state in which a current does not flow in either direction between the first electrode and the second electrode. 
 
     
     
       2. A semiconductor device, comprising:
 a semiconductor layer stack of a nitride semiconductor or a silicon carbide semiconductor formed on a substrate and having a channel region; 
 a first electrode and a second electrode formed spaced apart from each other on the semiconductor layer stack; and 
 a first gate electrode formed between the first electrode and the second electrode, and a second gate electrode formed between the first gate electrode and the second electrode, wherein: 
 a potential greater than the threshold voltage of the first gate electrode with reference to the potential of the first electrode is applied to the first gate electrode and a potential greater than the threshold voltage of the second gate electrode with reference to the potential of the second electrode is applied to the second gate electrode, whereby the semiconductor device is brought to a conductive state in which a current flows in both directions between the first electrode and the second electrode; and 
 a potential less than or equal to the threshold voltage of the first gate electrode with reference to the potential of the first electrode is applied to the first gate electrode and a potential less than or equal to the threshold voltage of the second gate electrode with reference to the potential of the second electrode is applied to the second gate electrode, whereby the semiconductor device is brought to a non-conductive state in which a current does not flow in either direction between the first electrode and the second electrode. 
 
     
     
       3. The semiconductor device of  claim 1 , wherein a potential greater than the threshold voltage of the first gate electrode with reference to the potential of the first electrode is applied to the first gate electrode and a potential greater than the threshold voltage of the second gate electrode with reference to the potential of the second electrode is applied to the second gate electrode, whereby the semiconductor device is brought to a conductive state in which a current flows in both directions between the first electrode and the second electrode. 
     
     
       4. The semiconductor device of  claim 1 , further comprising a first control layer having a p-type conductivity formed between the semiconductor layer stack and the first gate electrode. 
     
     
       5. The semiconductor device of claim  1  2 further comprising a first control layer having a p-type conductivity formed between the semiconductor layer stack and the first gate electrode. 
     
     
       6. The semiconductor device of  claim 4 , wherein the semiconductor device has a mode of operation in which a positive voltage with reference to the potential of the first electrode is applied to the first gate electrode to thereby inject holes into the channel region. 
     
     
       7. The semiconductor device of  claim 5 , wherein the semiconductor device has a mode of operation in which a positive voltage with reference to the potential of the first electrode is applied to the first gate electrode to thereby inject holes into the channel region. 
     
     
       8. The semiconductor device of  claim 4 , wherein the semiconductor device has a mode of operation in which a voltage greater than or equal to a built-in potential of a pn junction formed by the first control layer and the semiconductor layer stack is applied between the first gate electrode and the first electrode. 
     
     
       9. The semiconductor device of  claim 5 , wherein the semiconductor device has a mode of operation in which a voltage greater than or equal to a built-in potential of a pn junction formed by the first control layer and the semiconductor layer stack is applied between the first gate electrode and the first electrode. 
     
     
       10. The semiconductor device of  claim 4 , wherein a threshold voltage of the first gate electrode and that of the second gate electrode are different from each other. 
     
     
       11. The semiconductor device of  claim 10 , wherein the second gate electrode is in a Schottky junction with the semiconductor layer stack. 
     
     
       12. The semiconductor device of  claim 11 , wherein:
 the semiconductor layer stack includes a depressed portion; and 
 the second gate electrode is in contact with a bottom surface of the depressed portion. 
 
     
     
       13. The semiconductor device of  claim 4 , further comprising a second control layer having a p-type conductivity formed between the semiconductor layer stack and the second gate electrode. 
     
     
       14. The semiconductor device of  claim 5 , further comprising a second control layer having a p-type conductivity formed between the semiconductor layer stack and the second gate electrode. 
     
     
       15. The semiconductor device of  claim 8 , further comprising a second control layer having a p-type conductivity formed between the semiconductor layer stack and the second gate electrode, wherein the semiconductor device has a mode of operation in which a voltage greater than or equal to a built-in potential of a pn junction formed by the second control layer and the semiconductor layer stack is applied between the second gate electrode and the first electrode. 
     
     
       16. The semiconductor device of  claim 9 , further comprising a second control layer having a p-type conductivity formed between the semiconductor layer stack and the second gate electrode, wherein the semiconductor device has a mode of operation in which a voltage greater than or equal to a built-in potential of a pn junction formed by the second control layer and the semiconductor layer stack is applied between the second gate electrode and the first electrode. 
     
     
       17. The semiconductor device of  claim 13 , wherein:
 an uppermost layer of the semiconductor layer stack includes a first portion, and a second portion having a thickness smaller than that of the first portion; and 
 the first control layer and the second control layer are formed on the first portion. 
 
     
     
       18. The semiconductor device of  claim 14 , wherein:
 an uppermost layer of the semiconductor layer stack includes a first portion, and a second portion having a thickness smaller than that of the first portion; and 
 the first control layer and the second control layer are formed on the first portion. 
 
     
     
       19. The semiconductor device of  claim 17 , wherein:
 an uppermost layer of the semiconductor layer stack includes a third portion having a thickness less than or equal to that of the second portion; and 
 the first control layer and the second control layer is formed on the first portion and the third portion. 
 
     
     
       20. The semiconductor device of  claim 18 , wherein:
 an uppermost layer of the semiconductor layer stack includes a third portion having a thickness less than or equal to that of the second portion; and 
 the first control layer and the second control layer is formed on the first portion and the third portion. 
 
     
     
       21. The semiconductor device of  claim 13 , wherein:
 the semiconductor layer stack includes a first semiconductor layer, a second semiconductor layer having a band-gap larger than that of the first semiconductor layer, and an etching absorbing layer, wherein the layers are formed in this order from bottom; and 
 the etching absorbing layer is the uppermost layer of the semiconductor layer stack. 
 
     
     
       22. The semiconductor device of  claim 14 , wherein:
 the semiconductor layer stack includes a first semiconductor layer, a second semiconductor layer having a band-gap larger than that of the first semiconductor layer, and an etching absorbing layer, wherein the layers are formed in this order from bottom; and 
 the etching absorbing layer is the uppermost layer of the semiconductor layer stack. 
 
     
     
       23. The semiconductor device of  claim 13 , further comprising a high resistance layer formed on the semiconductor layer stack in a region between the first control layer and the second control layer, the high resistance layer having a resistance higher than that of the first control layer and the second control layer. 
     
     
       24. The semiconductor device of  claim 23 , wherein the high resistance layer is of a gallium oxide. 
     
     
       25. The semiconductor device of  claim 22 , wherein the high resistance layer is a layer containing boron. 
     
     
       26. The semiconductor device of  claim 13 , further comprising an undoped semiconductor layer formed on the semiconductor layer stack,
 wherein the first control layer and the second control layer are p-type impurity-diffused regions selectively formed in the undoped semiconductor layer. 
 
     
     
       27. The semiconductor device of  claim 13 , further comprising an oxide film layer having an opening formed on the semiconductor layer stack,
 wherein the first control layer and the second control layer are formed so as to be in contact with the semiconductor layer stack exposed through the opening. 
 
     
     
       28. The semiconductor device of  claim 14 , further comprising an undoped semiconductor layer formed on the semiconductor layer stack,
 wherein the first control layer and the second control layer are p-type impurity-diffused regions selectively formed in the undoped semiconductor layer. 
 
     
     
       29. The semiconductor device of  claim 14 , wherein further comprising an oxide film layer having an opening formed on the semiconductor layer stack,
 wherein the first control layer and the second control layer are formed so as to be in contact with the semiconductor layer stack exposed through the opening. 
 
     
     
       30. The semiconductor device of  claim 8 , wherein an interval between the first gate electrode and the second gate electrode is larger than that between the first electrode and the first gate electrode, and is larger than that between the second electrode and the second gate electrode. 
     
     
       31. The semiconductor device of  claim 9 , wherein an interval between the first gate electrode and the second gate electrode is larger than that between the first electrode and the first gate electrode, and is larger than that between the second electrode and the second gate electrode. 
     
     
       32. The semiconductor device of  claim 11 , wherein:
 a threshold voltage of the second gate electrode of the semiconductor element is greater than or equal to 0 V; and 
 the second electrode and the second gate electrode are electrically shorted with each other. 
 
     
     
       33. The semiconductor device of  claim 12 , wherein:
 a threshold voltage of the second gate electrode of the semiconductor element is greater than or equal to 0 V; and 
 the second electrode and the second gate electrode are electrically shorted with each other. 
 
     
     
       34. The semiconductor device of  claim 13 , wherein:
 a threshold voltage of the second gate electrode of the semiconductor element is greater than or equal to 0 V; and 
 the second electrode and the second gate electrode are electrically shorted with each other. 
 
     
     
       35. The semiconductor device of  claim 8 , wherein:
 the semiconductor layer stack includes a first semiconductor layer and a second semiconductor layer which are layered in this order from a side of the substrate; 
 the second semiconductor layer has a bandgap larger than that of the first semiconductor layer; and 
 the channel region is an interface region between the first semiconductor layer and the second semiconductor layer. 
 
     
     
       36. The semiconductor device of  claim 35 , wherein the first semiconductor layer and the second semiconductor layer contain at least one of gallium nitride and aluminum gallium nitride. 
     
     
       37. A semiconductor device, comprising:
 a substrate; 
 a semiconductor layer stack of a nitride semiconductor or a silicon carbide semiconductor formed on a disposed above the substrate and, the semiconductor layer stack having a channel region; 
 a first electrode and a second electrode formed disposed spaced apart from each other on the semiconductor layer stack; 
 a first gate electrode disposed between the first electrode and the second electrode; 
 a first control layer having a p-type conductivity formed disposed between the semiconductor layer stack and the first gate electrode; and 
 a third control second layer having a p-type conductivity formed disposed between the semiconductor layer stack and the second electrode. 
 
     
     
       38. A bidirectional switch, comprising:
 a semiconductor layer stack of a nitride semiconductor or a silicon carbide semiconductor formed on a substrate and having a channel region; 
 a first electrode and a second electrode formed spaced apart from each other on the semiconductor layer stack; 
 a first gate electrode formed between the first electrode and the second electrode, and a second gate electrode formed between the first gate electrode and the second electrode; and 
 a control section for controlling a voltage applied to the first gate electrode and second gate electrode, wherein: 
 in a conductive state in which a current flows in both directions between the first electrode and the second electrode, the control section applies, to the first gate electrode, a voltage higher than a threshold voltage of the first gate electrode with reference to a potential of the first electrode, and applies, to the second gate electrode, a voltage higher than a threshold voltage of the second gate electrode with reference to a potential of the second electrode; and 
 in a non-conductive state in which a current does not flow in either direction between the first electrode and the second electrode, the control section applies, to the first gate electrode, a voltage less than or equal to the threshold voltage of the first gate electrode with reference to the potential of the first electrode, and applies, to the second gate electrode, a voltage less than or equal to the threshold voltage of the second gate electrode with reference to the potential of the second electrode. 
 
     
     
       39. The bidirectional switch of  claim 38 , the control section including:
 a first variable power supply for applying a voltage between the first electrode and the first gate electrode; and 
 a second variable power supply for applying a voltage between the second electrode and the second gate electrode. 
 
     
     
       40. The bidirectional switch of  claim 38 , wherein:
 the semiconductor element is of a normally-off type; 
 the control section includes:
 a first power supply for applying a voltage higher than the threshold voltage of the first gate electrode between the first electrode and the first gate electrode; 
 a second power supply for applying a voltage higher than the threshold voltage of the second gate electrode between the second electrode and the second gate electrode; 
 a first gate driving circuit for connecting the first power supply between the first electrode and the first gate electrode in the conductive state, and electrically connecting the first electrode and the first gate electrode with each other in the non-conductive state; and 
 a second gate driving circuit for connecting the second power supply between the second electrode and the second gate electrode in the conductive state, and electrically connecting the second electrode and the second gate electrode with each other in the non-conductive state. 
 
 
     
     
       41. The bidirectional switch of  claim 40 , wherein the second gate driving circuit includes a circuit for electrically insulating the second control signal from the potential of the second electrode. 
     
     
       42. The bidirectional switch of  claim 41 , wherein the circuit includes a photocoupler. 
     
     
       43. The bidirectional switch of  claim 38 , wherein:
 the semiconductor element is of a normally-on type; 
 the control section includes:
 a third power supply for applying a voltage less than or equal to the threshold voltage of the first gate electrode between the first electrode and the first gate electrode; 
 a fourth power supply for applying a voltage less than or equal to the threshold voltage of the second gate electrode between the second electrode and the second gate electrode; 
 a third gate driving circuit for electrically connecting the first electrode and the first gate electrode with each other in the conductive state, and connecting the third power supply between the first electrode and the first gate electrode in the non-conductive state; and 
 a fourth gate driving circuit for electrically connecting the second electrode and the second gate electrode with each other in the conductive state, and connecting the third power supply between the fourth electrode and the second gate electrode in the non-conductive state. 
 
 
     
     
       44. The bidirectional switch of  claim 38 , wherein the control section includes:
 a first power supply for applying a voltage higher than the threshold voltage of the first gate electrode between the first electrode and the first gate electrode; 
 a second power supply for applying a voltage higher than the threshold voltage of the second gate electrode between the second electrode and the second gate electrode; 
 a third power supply for applying a voltage less than or equal to the threshold voltage of the first gate electrode between the first electrode and the first gate electrode; 
 a fourth power supply for applying a voltage less than or equal to the threshold voltage of the second gate electrode between the second electrode and the second gate electrode; 
 a first gate driving circuit for connecting the first power supply between the first electrode and the first gate electrode in the conductive state, and connecting the third power supply between the first electrode and the first gate electrode in the non-conductive state; and 
 a second gate driving circuit for connecting the second power supply between the second electrode and the second gate electrode in the conductive state, and connecting the fourth power supply between the second electrode and the second gate electrode in the non-conductive state. 
 
     
     
       45. The bidirectional switch of  claim 38 , wherein:
 the control section includes:
 a first gate driving circuit; 
 a second gate driving circuit; 
 a driver power supply; 
 a capacitor; and 
 a charging circuit for charging the capacitor; 
 
 the charging circuit includes a charging switch circuit connected between the driver power supply and the capacitor and charging the capacitor by the driver power supply; 
 the first gate driving circuit connects the driver power supply between the first electrode and the first gate electrode in the conductive state, and connects the first electrode and the first gate electrode with each other in the non-conductive state; and 
 the second gate driving circuit connects the capacitor between the second electrode and the second gate electrode in the conductive state, and connects the second electrode and the second gate electrode with each other in the non-conductive state. 
 
     
     
       46. The bidirectional switch of  claim 45 , wherein the charging switch circuit includes a semiconductor switch, and a diode connected in series with the semiconductor switch. 
     
     
       47. The bidirectional switch of  claim 46 , wherein the semiconductor switch is a p-channel MOSFET or a PNP transistor. 
     
     
       48. The bidirectional switch of  claim 45 , wherein the charging circuit charges the capacitor when a voltage between the second electrode and the first electrode is smaller than a driving voltage. 
     
     
       49. The bidirectional switch of  claim 45 , wherein the control section includes:
 a first step-down circuit connected between the first gate driving circuit and the first gate electrode; and 
 a second step-down circuit connected between the second gate driving circuit and the second gate electrode. 
 
     
     
       50. The bidirectional switch of  claim 49 , wherein the first step-down circuit and the second step-down circuit each include a resistor element and a Zener diode. 
     
     
       51. The bidirectional switch of  claim 45 , wherein the second gate driving circuit includes a circuit for electrically insulating the second control signal from the potential of the second electrode. 
     
     
       52. The bidirectional switch of  claim 45 , wherein the second gate driving circuit includes a photocoupler for electrically insulating the second control signal from the potential of the second electrode. 
     
     
       53. The bidirectional switch of  claim 38 , wherein:
 the control section includes a transformer whose secondary side is connected to the second electrode and the second gate electrode; and 
 a control signal for controlling the second gate electrode is input to a primary side of the transformer. 
 
     
     
       54. The bidirectional switch of  claim 53 , wherein:
 the control section includes a pulsed current generating section connected to the primary side of the transformer for generating a pulsed current; and 
 the second control signal is input to the transformer via the pulsed current generating section. 
 
     
     
       55. A method for driving a semiconductor device including a semiconductor element, the semiconductor element including a first electrode, a first gate electrode, a second gate electrode and a second electrode formed in this order while being spaced apart from one another on a semiconductor layer stack, which is formed on a substrate, the method comprising the steps of:
 a step of applying a potential greater than a threshold voltage of the first gate electrode with reference to a potential of the first electrode to the first gate electrode and applying a potential less than or equal to a threshold voltage of the second gate electrode with reference to a potential of the second electrode to the second gate electrode, whereby the semiconductor device is brought to a reverse-blocking state in which a current flows from the second electrode to the first electrode but not from the first electrode to the second electrode; and 
 a step of applying a potential less than or equal to the threshold voltage of the first gate electrode with reference to the potential of the first electrode to the first gate electrode and applying a potential less than or equal to the threshold voltage of the second gate electrode with reference to the potential of the second electrode to the second gate electrode, whereby the semiconductor device is brought to a non-conductive state in which a current does not flow in either direction between the first electrode and the second electrode. 
 
     
     
       56. A method for driving a semiconductor device including a semiconductor element, the semiconductor element including a first electrode, a first gate electrode, a second gate electrode and a second electrode formed in this order while being spaced apart from one another on a semiconductor layer stack, which is formed on a substrate, the method comprising the steps of:
 a step of applying a potential greater than the threshold voltage of the first gate electrode with reference to the potential of the first electrode to the first gate electrode and applying a potential greater than the threshold voltage of the second gate electrode with reference to the potential of the second electrode to the second gate electrode, whereby the semiconductor device is brought to a conductive state in which a current flows in both directions between the first electrode and the second electrode; and 
 a step of applying a potential less than or equal to the threshold voltage of the first gate electrode with reference to the potential of the first electrode to the first gate electrode and applying a potential less than or equal to the threshold voltage of the second gate electrode with reference to the potential of the second electrode to the second gate electrode, whereby the semiconductor device is brought to a non-conductive state in which a current does not flow in either direction between the first electrode and the second electrode. 
 
     
     
       57. The method for driving a semiconductor device of  claim 55 , further comprising a step of applying a potential greater than the threshold voltage of the first gate electrode with reference to the potential of the first electrode to the first gate electrode and applying a potential greater than the threshold voltage of the second gate electrode with reference to the potential of the second electrode to the second gate electrode, whereby the semiconductor device is brought to a conductive state in which a current flows in both directions between the first electrode and the second electrode. 
     
     
       58. The semiconductor device of claim 37, wherein:
 the second electrode includes a first side and a second side in a cross-sectional view, the first side being disposed between the first gate electrode and the second side,   the second layer includes a third side and a fourth side in the cross-sectional view, the third side being disposed between the first gate electrode and the fourth side, and   the third side is disposed between the first gate electrode and the first side.   
     
     
       59. The semiconductor device of claim 37, wherein:
 the semiconductor layer stack includes a first region having a first thickness and a second region having a second thickness, the first thickness being greater than the second thickness,   the first layer and the second layer are disposed on the first region, and   at least a portion of the second region is disposed between the first layer and the second layer.   
     
     
       60. The semiconductor device of claim 59, wherein:
 the semiconductor layer stack includes a third region having a third thickness, the third thickness being smaller than the second thickness, and   the first layer is disposed on the first region and the third region.   
     
     
       61. The semiconductor device of claim 60, wherein a threshold voltage of the first gate electrode is determined by a thickness of the semiconductor layer stack disposed in the third region. 
     
     
       62. A semiconductor device comprising:
 a substrate;   a semiconductor layer stack of a nitride semiconductor or a silicon carbide semiconductor disposed above the substrate, the semiconductor layer stack having a channel region;   a first electrode disposed on the semiconductor layer stack;   a second electrode disposed on the semiconductor layer stack;   a first layer having a p-type conductivity, the first layer disposed on the semiconductor layer stack and disposed between the first electrode and the second electrode;   a second layer having a p-type conductivity, the second layer disposed on the semiconductor layer stack and disposed between the first layer and the second electrode;   a third electrode disposed on the first layer; and   a fourth electrode disposed on the second layer, wherein:   the semiconductor layer stack includes a first region having a first thickness and a second region having a second thickness, the first thickness being greater than the second thickness,   the first layer and the second layer are disposed on the first region, and   at least a portion of the second region is disposed between the first layer and the second layer.   
     
     
       63. The semiconductor device of claim 62, wherein the third electrode is electrically connected to the fourth electrode. 
     
     
       64. The semiconductor device of claim 63, wherein:
 the fourth electrode includes a first side and a second side in a cross-sectional view, the first side being disposed between the third electrode and the second side,   the second layer includes a third side and a fourth side in the cross-sectional view, the third side being disposed between the third electrode and the fourth side, and   the third side is disposed between the third electrode and the first side.   
     
     
       65. The semiconductor device of claim 63, wherein:
 the first electrode is a source electrode,   the second electrode is a drain electrode,   the third electrode is a gate electrode, and   the semiconductor device is a three-terminal device.   
     
     
       66. The semiconductor device of claim 62, wherein:
 the third electrode has a first threshold voltage, and   the fourth electrode has a second threshold voltage different from the first threshold voltage.   
     
     
       67. The semiconductor device of claim 62, wherein:
 the semiconductor layer stack includes a third region having a third thickness, the third thickness being smaller than the second thickness, and   the first layer is disposed on the first region and the third region.   
     
     
       68. The semiconductor device of claim 67, wherein a threshold voltage of the third electrode is determined by a thickness of the semiconductor layer stack disposed in the third region. 
     
     
       69. A semiconductor device comprising:
 a substrate;   a semiconductor layer stack of a nitride semiconductor or a silicon carbide semiconductor disposed above the substrate, the semiconductor layer stack having a channel region;   a first electrode disposed on the semiconductor layer stack;   a second electrode disposed on the semiconductor layer stack;   a third electrode disposed on the semiconductor layer stack and disposed between the first electrode and the second electrode; and   a fourth electrode disposed on the semiconductor layer stack and disposed between the third electrode and the second electrode,   wherein the fourth electrode is electrically connected to the second electrode.   
     
     
       70. The semiconductor device of claim 69, wherein:
 the first electrode is a source electrode,   the second electrode is a drain electrode,   the third electrode is a gate electrode, and   the semiconductor device is a three-terminal device.   
     
     
       71. The semiconductor device of claim 69, further comprising:
 a layer having a p-type conductivity disposed on the semiconductor layer stack,   wherein the third electrode is disposed on the layer.   
     
     
       72. The semiconductor device of claim 69, further comprising:
 a layer having a p-type conductivity disposed on the semiconductor layer stack,   wherein the fourth electrode is disposed on the layer.   
     
     
       73. The semiconductor device of claim 69, wherein:
 the fourth electrode includes a first side and a second side in a cross-sectional view, the first side being disposed between the third electrode and the second side,   the second layer includes a third side and a fourth side in the cross-sectional view, the third side being disposed between the third electrode and the fourth side, and   the third side is disposed between the third electrode and the first side.   
     
     
       74. The semiconductor device of claim 69, wherein the fourth electrode forms a Schottky junction with the semiconductor layer stack. 
     
     
       75. The semiconductor device of claim 71, wherein:
 the third electrode has a first threshold voltage, and   the fourth electrode has a second threshold voltage different from the first threshold voltage.   
     
     
       76. The semiconductor device of claim 72, wherein:
 the third electrode has a first threshold voltage, and   the fourth electrode has a second threshold voltage different from the first threshold voltage.   
     
     
       77. A semiconductor device comprising:
 a substrate;   a semiconductor layer stack of a nitride semiconductor or a silicon carbide semiconductor disposed above the substrate, the semiconductor layer stack having a channel region;   a first electrode disposed on the semiconductor layer stack;   a second electrode disposed on the semiconductor layer stack;   a third electrode disposed on the semiconductor layer stack and disposed between the first electrode and the second electrode;   a layer having a p-type conductivity, the layer disposed on the semiconductor layer stack and disposed between the third electrode and the second electrode; and   a fourth electrode disposed on the layer, wherein:   the layer forms a pn junction with the semiconductor layer stack, and   a voltage higher than a built-in voltage of the pn junction is applied to the fourth electrode.   
     
     
       78. The semiconductor device of claim 77, wherein the third electrode is electrically connected to the fourth electrode. 
     
     
       79. The semiconductor device of claim 78, wherein:
 the fourth electrode includes a first side and a second side in a cross-sectional view, the first side being disposed between the third electrode and the second side,   the layer includes a third side and a fourth side in the cross-sectional view, the third side being disposed between the third electrode and the fourth side, and   the third side is disposed between the third electrode and the first side.   
     
     
       80. The semiconductor device of claim 77, wherein:
 the third electrode has a first threshold voltage, and   the fourth electrode has a second threshold voltage different from the first threshold voltage.   
     
     
       81. The semiconductor device of claim 77, wherein:
 the semiconductor layer stack includes a first region having a first thickness and a second region having a second thickness, the first thickness being greater than the second thickness,   the layer is disposed on the first region, and   at least a portion of the second region is disposed between the first gate electrode and the layer.   
     
     
       82. A semiconductor device, comprising:
 a substrate;   a semiconductor layer stack of a nitride semiconductor or a silicon carbide semiconductor disposed above the substrate, the semiconductor layer stack having a channel region;   a first electrode and a second electrode disposed spaced apart from each other on the semiconductor layer stack;   a first gate electrode disposed on the semiconductor layer stack and disposed between the first electrode and the second electrode; and   a layer having a p-type conductivity and disposed between the semiconductor layer stack and the second electrode.   
     
     
       83. The semiconductor device of claim 82, wherein:
 the second electrode includes a first side and a second side in a cross-sectional view, the first side being disposed between the first gate electrode and the second side,   the layer includes a third side and a fourth side in the cross-sectional view, the third side being disposed between the first gate electrode and the fourth side, and   the third side is disposed between the first gate electrode and the first side.   
     
     
       84. The semiconductor device of claim 82, wherein:
 the semiconductor layer stack includes a first region having a first thickness and a second region having a second thickness, the first thickness being greater than the second thickness,   the layer is disposed on the first region, and   at least a portion of the second region is disposed between the first gate electrode and the layer.