Power-saving circuit and method for a digital video display device

Abstract

A power-saving circuit for a digital video display device includes a TMDS driving unit converting a TMDS data signal and a TMDS clock signal, a display driving unit driving a display unit based on the horizontal/vertical synchronous signals and the digital video signal input from the TMDS driving unit, a clock signal detecting unit outputting a first or a second level of a clock detecting signal depending on the TMDS clock signal, a controller outputting a first-level of a power-saving signal when the first level clock detecting signal is input, and outputting a second level of power-saving signal when the second level clock detecting signal is input, and a power supply unit supplying a voltage to respective components, and cutting off the supply of the voltage to respective components depending on the level of the power-saving signal or the clock detecting signal.

What is claimed is: 
     
       1. A power-saving circuit for a digital video display device, comprising:
 a transmission minimized differential signaling driving unit for converting a transmission minimized differential signaling data signal input together with a transmission minimized differential signaling clock signal to the transmission minimized differential signaling driving unit into horizontal and vertical synchronous signals and a digital video signal based on a transmission minimized differential signaling signal conversion mode;   a display driving unit for driving a display unit based on the horizontal and vertical synchronous signals and the digital video signal input from the transmission minimized differential signaling driving unit;   a clock signal detecting unit for outputting a first level of a clock detecting signal when the transmission minimized differential signaling clock signal is not input to the transmission minimized differential signaling driving unit and for outputting a second level of the clock detecting signal when the transmission minimized differential signaling clock signal is input to the transmission minimized differential signaling driving unit;   a controller for outputting a first level of a power-saving signal when the first level of the clock detecting signal is input to the controller from the clock signal detecting unit, and for outputting a second level of the power-saving signal when the second level of the clock detecting signal is input to the controller from the clock signal detecting unit; and   a power supply unit for supplying a voltage to the transmission minimized differential signaling driving unit, the controller, the clock signal detecting unit and the display driving unit, for cutting off the supply of the voltage except to the controller and the clock signal detecting unit when the first level of the power-saving signal is input to the power supply unit from the controller, and for providing the supply of the voltage to the transmission minimized differential signaling driving unit, the controller, the clock signal detecting unit and the display driving unit when the second level of the power-saving signal is input to the power supply unit from the controller.   
     
     
       2. The power-saving circuit as claimed in  claim 1 , further comprised of the clock signal detecting unit comprising:
 a first capacitor for removing direct current components of the transmission minimized differential signaling clock signal;   an amplifying transistor connected to the first capacitor for amplifying the transmission minimized differential signaling clock signal without the direct current components removed by the first capacitor to provide an amplified signal;   a first resistor connected to the base of the amplifying transistor for biasing the base of the amplifying transistor;   a second resistor connected to the collector of the amplifying transistor for biasing the collector of the amplifying transistor;   a switching transistor connected to the emitter and the collector of the amplifying transistor, the switching transistor being switched based on the amplified signal received from the amplifying transistor, and for outputting one of a low level signal and a high level signal through the collector of the switching transistor, the low level signal corresponding to the first level of the clock detecting signal and the high level signal corresponding to the second level of the clock detecting signal;   a third resistor connected to the collector of the switching transistor for biasing the collector of the switching transistor; and   a second capacitor connected to the emitter of the switching transistor, and a fourth resistor connected to the second capacitor and the collector of the switching transistor, the second capacitor and the fourth resistor for smoothing an output signal of the switching transistor, the output signal of the switching transistor corresponding to one of the first level of the clock detecting signal and the second level of the clock detecting signal.   
     
     
       3. The power-saving circuit as claimed in  claim 2 , further comprised of the first resistor of the clock signal detecting unit including a pair of resistors connected to the base of the amplifying transistor for biasing the base of the amplifying transistor. 
     
     
       4. A power-saving circuit for a digital video display device, comprising:
 a transmission minimized differential signaling driving unit for converting a transmission minimized differential signaling data signal input together with a transmission minimized differential signaling clock signal to the transmission minimized differential signaling driving unit into horizontal and vertical synchronous signals and a digital video signal based on a transmission minimized differential signaling signal conversion mode, for stopping a driving of an operation for signal converting when a first level of a power-down signal is input to the transmission minimized differential signaling driving unit, and for starting the driving of the operation for signal converting when a second level of the power-down signal is input to the transmission minimized differential signaling driving unit;   a display driving unit for driving a display unit based on the horizontal and vertical synchronous signals and the digital video signal input to the display driving unit from the transmission minimized differential signaling driving unit;   a clock signal detecting unit for outputting a first level of a clock detecting signal when the transmission minimized differential signaling clock signal is not input to the transmission minimized differential signaling driving unit and for outputting a second level of the clock detecting signal when the transmission minimized differential signaling clock signal is input to the transmission minimized differential signaling driving unit;   a controller for outputting the first level of the power-down signal to the transmission minimized differential signaling driving unit and for outputting a first level of a power-saving signal when the first level of clock detecting signal is input to the controller from the clock signal detecting unit, and for outputting the second level of the power-down signal to the transmission minimized differential signaling driving unit and for outputting a second level of the power-saving signal when the second level of the clock detecting signal is input to the controller from the clock signal detecting unit; and   a power supply unit for supplying a voltage to the transmission minimized differential signaling driving unit, the display driving unit, the clock signal detecting unit and the controller, for cutting off the supply of the voltage except to the controller, the transmission minimized differential signaling driving unit and the clock signal detecting unit when the first level of the power-saving signal is input to the power supply unit from the controller, and for providing the supply of the voltage to the transmission minimized differential signaling driving unit, the display driving unit, the clock signal detecting unit and the controller when the second level of power-saving signal is input to the power supply unit from the controller.   
     
     
       5. The power-saving circuit as claimed in  claim 4 , further comprised of the clock signal detecting unit comprising:
 a first capacitor for removing direct current components of the transmission minimized differential signaling clock signal;   an amplifying transistor connected to the first capacitor for amplifying the transmission minimized differential signaling clock signal without the direct current components removed by the first capacitor to provide an amplified signal;   a first resistor connected to the base of the amplifying transistor for biasing the base of the amplifying transistor;   a second resistor connected to the collector of the amplifying transistor for biasing the collector of the amplifying transistor;   a switching transistor connected to the emitter and the collector of the amplifying transistor, the switching transistor being switched based on the amplified signal received from the amplifying transistor, and for outputting one of a low level signal and a high level signal through the collector of the switching transistor, the low level signal corresponding to the first level of the clock detecting signal and the high level signal corresponding to the second level of the clock detecting signal;   a third resistor connected to the collector of the switching transistor for biasing the collector of the switching transistor; and   a second capacitor connected to the emitter of the switching transistor, and a fourth resistor connected to the second capacitor and the collector of the switching transistor, the second capacitor and the fourth resistor for smoothing an output signal of the switching transistor, the output signal of the switching transistor corresponding to one of the first level of the clock detecting signal and the second level of the clock detecting signal.   
     
     
       6. The power-saving circuit as claimed in  claim 5 , further comprised of the first resistor of the clock signal detecting unit including a pair of resistors connected to the base of the amplifying transistor for biasing the base of the amplifying transistor. 
     
     
       7. A power-saving circuit for a digital video display device, comprising:
 a transmission minimized differential signaling driving unit for converting a transmission minimized differential signaling data signal input together with a transmission minimized differential signaling clock signal to the transmission minimized differential signaling driving unit into horizontal and vertical synchronous signals and a digital video signal based on a transmission minimized differential signaling signal conversion mode;   a display driving unit for driving a display unit based on the horizontal and vertical synchronous signals and the digital video signal input to the display driving unit from the transmission minimized differential signaling driving unit;   a clock signal detecting unit for outputting a first level of a clock detecting signal when the transmission minimized differential signaling clock signal is not input to the transmission minimized differential signaling driving unit, and for outputting a second level of the clock detecting signal when the transmission minimized differential signaling clock signal is input to the transmission minimized differential signaling driving unit; and   a power supply unit for supplying a voltage to the transmission minimized differential signaling driving unit, the display driving unit and the clock signal detecting unit, for cutting off the supply of the voltage except to the clock signal detecting unit when the first level of the clock detecting signal is input to the power supply unit from the clock signal detecting unit, and for providing the supply of the voltage to the transmission minimized differential signaling driving unit, the display driving unit and the clock signal detecting unit when the second level of the clock detecting signal is input to the power supply unit from the clock signal detecting unit.   
     
     
       8. The power-saving circuit as claimed in  claim 7 , further comprised of the clock signal detecting unit comprising:
 a first capacitor for removing direct current components of the transmission minimized differential signaling clock signal;   an amplifying transistor connected to the first capacitor for amplifying the transmission minimized differential signaling clock signal without the direct current components removed by the first capacitor to provide an amplified signal;   a first resistor connected to the base of the amplifying transistor for biasing the base of the amplifying transistor;   a second resistor connected to the collector of the amplifying transistor for biasing the collector of the amplifying transistor;   a switching transistor connected to the emitter and the collector of the amplifying transistor, the switching transistor being switched based on the amplified signal received from the amplifying transistor, and for outputting one of a low level signal and a high level signal through the collector of the switching transistor, the low level signal corresponding to the first level of the clock detecting signal and the high level signal corresponding to the second level of the clock detecting signal;   a third resistor connected to the collector of the switching transistor for biasing the collector of the switching transistor; and   a second capacitor connected to the emitter of the switching transistor, and a fourth resistor connected to the second capacitor and the collector of the switching transistor, the second capacitor and the fourth resistor for smoothing an output signal of the switching transistor, the output signal of the switching transistor corresponding to one of the first level of the clock detecting signal and the second level of the clock detecting signal.   
     
     
       9. The power-saving circuit as claimed in  claim 8 , further comprised of the first resistor of the clock signal detecting unit including a pair of resistors connected to the base of the amplifying transistor for biasing the base of the amplifying transistor. 
     
     
       10. A power-saving circuit for a digital video display device, comprising:
 a transmission minimized differential signaling driving unit for converting a transmission minimized differential signaling data signal input together with a transmission minimized differential signaling clock signal to the transmission minimized differential signaling driving unit into horizontal and vertical synchronous signals and a digital video signal based on a transmission minimized differential signaling signal conversion mode, for stopping a driving of an operation for signal converting when a first level of a clock detecting signal is input to the transmission minimized differential signaling driving unit, and for starting the driving of the operation for signal converting when a second level of the clock detecting signal is input to the transmission minimized differential signaling driving unit;   a display driving unit for driving a display unit based on the horizontal and vertical synchronous signals and the digital video signal input to the display driving unit from the transmission minimized differential signaling driving unit;   a clock signal detecting unit for outputting the first level of the clock detecting signal to the transmission minimized differential signaling driving unit when the transmission minimized differential signaling clock signal is not input to the transmission minimized differential signaling driving unit, and for outputting the second level of the clock detecting signal to the transmission minimized differential signaling driving unit when the transmission minimized differential signaling clock signal is input to the transmission minimized differential signaling driving unit; and   a power supply unit for supplying a voltage to the transmission minimized differential signaling driving unit, the display driving unit, and the clock signal detecting unit, for cutting off the supply of the voltage except to the transmission minimized differential signaling driving unit and the clock signal detecting unit when the first level of the clock detecting signal is input to the power supply unit from the clock signal detecting unit, and for providing the supply of the voltage to the transmission minimized differential signaling driving unit, the display driving unit, and the clock signal detecting unit when the second level of the clock detecting signal is input to the power supply unit from the clock signal detecting unit.   
     
     
       11. The power-saving circuit as claimed in  claim 10 , further comprised of the clock signal detecting unit comprising:
 a first capacitor for removing direct current components of the transmission minimized differential signaling clock signal;   an amplifying transistor connected to the first capacitor for amplifying the transmission minimized differential signaling clock signal without the direct current components removed by the first capacitor to provide an amplified signal;   a first resistor connected to the base of the amplifying transistor for biasing the base of the amplifying transistor;   a second resistor connected to the collector of the amplifying transistor for biasing the collector of the amplifying transistor;   a switching transistor connected to the emitter and the collector of the amplifying transistor, the switching transistor being switched based on the amplified signal received from the amplifying transistor, and for outputting one of a low level signal and a high level signal through the collector of the switching transistor, the low level signal corresponding to the first level of the clock detecting signal and the high level signal corresponding to the second level of the clock detecting signal;   a third resistor connected to the collector of the switching transistor for biasing the collector of the switching transistor; and   a second capacitor connected to the emitter of the switching transistor, and a fourth resistor connected to the second capacitor and the collector of the switching transistor, the second capacitor and the fourth resistor for smoothing an output signal of the switching transistor, the output signal of the switching transistor corresponding to one of the first level of the clock detecting signal and the second level of the clock detecting signal.   
     
     
       12. The power-saving circuit as claimed in  claim 11 , further comprised of the first resistor of the clock signal detecting unit including a pair of resistors connected to the base of the amplifying transistor for biasing the base of the amplifying transistor. 
     
     
       13. A power-saving method for a digital video display device, comprising the steps of:
 converting by a transmission minimized differential signaling driving unit a transmission minimized differential signaling data signal input together with a transmission minimized differential signaling clock signal to the transmission minimized differential signaling driving unit into horizontal and vertical synchronous signals and a digital video signal based on a transmission minimized differential signaling signal conversion mode;   driving by a display driving unit a display unit based on the horizontal and vertical synchronous signals and the digital video signal input from the transmission minimized differential signaling driving unit;   outputting by a clock signal detecting unit a first level of a clock detecting signal when the transmission minimized differential signaling clock signal is not input to the transmission minimized differential signaling driving unit and outputting by the clock signal detecting unit a second level of the clock detecting signal when the transmission minimized differential signaling clock signal is input to the transmission minimized differential signaling driving unit;   outputting by a controller a first level of a power-saving signal when the first level of the clock detecting signal is input to the controller from the clock signal detecting unit, and outputting by the controller a second level of the power-saving signal when the second level of the clock detecting signal is input to the controller from the clock signal detecting unit; and   supplying by a power supply unit a voltage to the transmission minimized differential signaling driving unit, the controller, the clock signal detecting unit and the display driving unit, cutting off by the power supply unit the supply of the voltage except to the controller and the clock signal detecting unit when the first level of the power-saving signal is input to the power supply unit from the controller, and providing by the power supply unit the supply of the voltage to the transmission minimized differential signaling driving unit, the controller, the clock signal detecting unit and the display driving unit when the second level of the power-saving signal is input to the power supply unit from the controller.   
     
     
       14. A power-saving method for a digital video display device, comprising the steps of:
 converting by a transmission minimized differential signaling driving unit a transmission minimized differential signaling data signal input together with a transmission minimized differential signaling clock signal to the transmission minimized differential signaling driving unit into horizontal and vertical synchronous signals and a digital video signal based on a transmission minimized differential signaling signal conversion mode, stopping by the transmission minimized differential signaling driving unit a driving of an operation for signal converting when a first level of a power-down signal is input to the transmission minimized differential signaling driving unit, and starting by the transmission minimized differential signaling driving unit the driving of the operation for signal converting when a second level of the power-down signal is input to the transmission minimized differential signaling driving unit;   driving by a display driving unit a display unit based on the horizontal and vertical synchronous signals and the digital video signal input to the display driving unit from the transmission minimized differential signaling driving unit;   outputting by a clock signal detecting unit a first level of a clock detecting signal when the transmission minimized differential signaling clock signal is not input to the transmission minimized differential signaling driving unit and outputting by the clock signal detecting unit a second level of the clock detecting signal when the transmission minimized differential signaling clock signal is input to the transmission minimized differential signaling driving unit;   outputting by a controller the first level of the power-down signal to the transmission minimized differential signaling driving unit and outputting by the controller a first level of a power-saving signal when the first level of clock detecting signal is input to the controller from the clock signal detecting unit, and outputting by the controller the second level of the power-down signal to the transmission minimized differential signaling driving unit and outputting by the controller a second level of the power-saving signal when the second level of the clock detecting signal is input to the controller from the clock signal detecting unit; and   supplying by a power supply unit a voltage to the transmission minimized differential signaling driving unit, the display driving unit, the clock signal detecting unit and the controller, cutting off by the power supply unit the supply of the voltage except to the controller, the transmission minimized differential signaling driving unit and the clock signal detecting unit when the first level of the power-saving signal is input to the power supply unit from the controller, and providing by the power supply unit the supply of the voltage to the transmission minimized differential signaling driving unit, the display driving unit, the clock signal detecting unit and the controller when the second level of power-saving signal is input to the power supply unit from the controller.   
     
     
       15. A power-saving method for a digital video display device, comprising the steps of:
 converting by a transmission minimized differential signaling driving unit a transmission minimized differential signaling data signal input together with a transmission minimized differential signaling clock signal to the transmission minimized differential signaling driving unit into horizontal and vertical synchronous signals and a digital video signal based on a transmission minimized differential signaling signal conversion mode;   driving by a display driving unit a display unit based on the horizontal and vertical synchronous signals and the digital video signal input to the display driving unit from the transmission minimized differential signaling driving unit;   outputting by a clock signal detecting unit a first level of a clock detecting signal when the transmission minimized differential signaling clock signal is not input to the transmission minimized differential signaling driving unit, and outputting by the clock signal detecting unit a second level of the clock detecting signal when the transmission minimized differential signaling clock signal is input to the transmission minimized differential signaling driving unit; and   supplying by a power supply unit a voltage to the transmission minimized differential signaling driving unit, the display driving unit and the clock signal detecting unit, cutting off by the power supply unit the supply of the voltage except to the clock signal detecting unit when the first level of the clock detecting signal is input to the power supply unit from the clock signal detecting unit, and providing by the power supply unit the supply of the voltage to the transmission minimized differential signaling driving unit, the display driving unit and the clock signal detecting unit when the second level of the clock detecting signal is input to the power supply unit from the clock signal detecting unit.   
     
     
       16. A power-saving method for a digital video display device, comprising the steps of:
 converting by a transmission minimized differential signaling driving unit a transmission minimized differential signaling data signal input together with a transmission minimized differential signaling clock signal to the transmission minimized differential signaling driving unit into horizontal and vertical synchronous signals and a digital video signal based on a transmission minimized differential signaling signal conversion mode, stopping by the transmission minimized differential signaling driving unit a driving of an operation for signal converting when a first level of a clock detecting signal is input to the transmission minimized differential signaling driving unit, and starting by the transmission minimized differential signaling driving unit the driving of the operation for signal converting when a second level of the clock detecting signal is input to the transmission minimized differential signaling driving unit;   driving by a display driving unit a display unit based on the horizontal and vertical synchronous signals and the digital video signal input to the display driving unit from the transmission minimized differential signaling driving unit;   outputting by a clock signal detecting unit the first level of the clock detecting signal to the transmission minimized differential signaling driving unit when the transmission minimized differential signaling clock signal is not input to the transmission minimized differential signaling driving unit, and outputting by the clock signal detecting unit the second level of the clock detecting signal to the transmission minimized differential signaling driving unit when the transmission minimized differential signaling clock signal is input to the transmission minimized differential signaling driving unit; and   supplying by a power supply unit a voltage to the transmission minimized differential signaling driving unit, the display driving unit, and the clock signal detecting unit, cutting off by the power supply unit the supply of the voltage except to the transmission minimized differential signaling driving unit and the clock signal detecting unit when the first level of the clock detecting signal is input to the power supply unit from the clock signal detecting unit, and providing by the power supply unit the supply of the voltage to the transmission minimized differential signaling driving unit, the display driving unit, and the clock signal detecting unit when the second level of the clock detecting signal is input to the power supply unit from the clock signal detecting unit.   
     
     
       17. A power-saving circuit for a digital video display device having a transmission minimized differential signaling driving unit having a signal conversion mode for converting a transmission minimized differential signaling data signal and a transmission minimized differential signaling clock signal input to the transmission minimized differential signaling driving unit into horizontal and vertical synchronous signals and a digital video signal, a display driving unit for driving a display unit based on the horizontal and vertical synchronous signals and the digital video signal input from the transmission minimized differential signaling driving unit and a power supply unit for supplying a voltage to the transmission minimized differential signaling driving unit and the display driving unit, said power-saving circuit comprising:
 a clock signal detecting unit outputting a first level of a clock detecting signal when the transmission minimized differential signaling clock signal is not input to the transmission minimized differential signaling driving unit and outputting a second level of the clock detecting signal when the transmission minimized differential signaling clock signal is input to the transmission minimized differential signaling driving unit;   said power supply unit cutting off the supply of the voltage to at least one of the transmission minimized differential signaling driving unit and the display driving unit when the clock signal detecting unit outputs the first level of the clock detecting signal, and providing the supply of the voltage to the transmission minimized differential signaling driving unit and the display driving unit when the clock signal detecting unit outputs the second level of the clock detecting signal.   
     
     
       18. The power-saving circuit as claimed in  claim 17 , further comprised of the clock signal detecting unit comprising:
 a first capacitor removing direct current components of the transmission minimized differential signaling clock signal;   an amplifying transistor connected to the first capacitor amplifying the transmission minimized differential signaling clock signal without the direct current components removed by the first capacitor to provide an amplified signal;   a first resistor connected to the base of the amplifying transistor biasing the base of the amplifying transistor;   a second resistor connected to the collector of the amplifying transistor biasing the collector of the amplifying transistor;   a switching transistor connected to the emitter and the collector of the amplifying transistor, the switching transistor being switched based on the amplified signal received from the amplifying transistor, and outputting one of a low level signal and a high level signal through the collector of the switching transistor, the low level signal corresponding to the first level of the clock detecting signal and the high level signal corresponding to the second level of the clock detecting signal;   a third resistor connected to the collector of the switching transistor biasing the collector of the switching transistor; and   a second capacitor connected to the emitter of the switching transistor, and a fourth resistor connected to the second capacitor and the collector of the switching transistor, the second capacitor and the fourth resistor smoothing an output signal of the switching transistor, the output signal of the switching transistor corresponding to one of the first level of the clock detecting signal and the second level of the clock detecting signal.   
     
     
       19. The power-saving circuit as claimed in  claim 18 , further comprised of the first resistor of the clock signal detecting unit including a pair of resistors connected to the base of the amplifying transistor biasing the base of the amplifying transistor. 
     
     
       20. The power-saving circuit as claimed in  claim 17 , said power supply unit cutting off the supply of the voltage to both the transmission minimized differential signaling driving unit and the display driving unit when the clock signal detecting unit outputs the first level of the clock detecting signal. 
     
     
       21. The power-saving circuit as claimed in  claim 17 , further comprising:
 a controller outputting a first level of a power-saving signal when the first level of the clock detecting signal is input to the controller from the clock signal detecting unit, and outputting a second level of the power-saving signal when the second level of the clock detecting signal is input to the controller from the clock signal detecting unit;   said power supply unit further supplying a voltage to the controller and the clock signal detecting unit, cutting off the supply of the voltage to both the transmission minimized differential signaling driving unit and the display driving unit, but not to the controller and the clock signal detecting unit, when the first level of the power-saving signal is input to the power supply unit from the controller; and   said power supply unit re-supplying the voltage to the transmission minimized differential signaling driving unit and the display driving unit when the second level of the power-saving signal is input to the power supply unit from the controller.   
     
     
       22. The power-saving circuit as claimed in  claim 17 , further comprising:
 a controller outputting a first level of a power-down signal to the transmission minimized differential signaling driving unit and outputting a first level of a power-saving signal to the power supply unit when the first level of clock detecting signal is input to the controller from the clock signal detecting unit, said transmission minimized differential signaling driving unit stopping the signal conversion mode in response to said first level of a power-down signal;   said controller outputting a second level of the power-down signal to the transmission minimized differential signaling driving unit and outputting a second level of the power-saving signal to the power supply unit when the second level of the clock detecting signal is input to the controller from the clock signal detecting unit, said transmission minimized differential signaling driving unit starting the signal conversion mode in response to said second level of the power-down signal; and   said power supply unit further supplying a voltage to the clock signal detecting unit and the controller, cutting off the supply of the voltage to said display driving unit, but not to the controller, the transmission minimized differential signaling driving unit and the clock signal detecting unit, when the first level of the power-saving signal is input to the power supply unit from the controller, and re-supplying of the voltage to the display driving unit when the second level of power-saving signal is input to the power supply unit from the controller.   
     
     
       23. The power-saving circuit as claimed in  claim 17 , further comprising:
 a controller outputting a first level of a power-saving signal when the first level of the clock detecting signal is input to the controller from the clock signal detecting unit, and outputting a second level of the power-saving signal when the second level of the clock detecting signal is input to the controller from the clock signal detecting unit;   said power supply unit further supplying a voltage to the controller and the clock signal detecting unit, cutting off the supply of the voltage to said at least one of the transmission minimized differential signaling driving unit and the display driving unit, but not to the controller and the clock signal detecting unit, when the first level of the power-saving signal is input to the power supply unit from the controller; and   said power supply unit re-supplying the voltage to the transmission minimized differential signaling driving unit and the display driving unit when the second level of the power-saving signal is input to the power supply unit from the controller.   
     
     
       24. The power-saving circuit as claimed in  claim 23 , further comprising:
 said controller outputting a first level of a power-down signal to the transmission minimized differential signaling driving unit when the first level of clock detecting signal is input to the controller from the clock signal detecting unit, said transmission minimized differential signaling driving unit stopping the signal conversion mode in response to said first level of a power-down signal; and   said controller outputting a second level of the power-down signal to the transmission minimized differential signaling driving unit when the second level of the clock detecting signal is input to the controller from the clock signal detecting unit, said transmission minimized differential signaling driving unit starting the signal conversion mode in response to said second level of the power-down signal.   
     
     
       25. The power-saving circuit as claimed in  claim 17 , further comprising:
 said clock signal detecting unit outputting the first level of the clock detecting signal to the transmission minimized differential signaling driving unit when the transmission minimized differential signaling clock signal is not input to the transmission minimized differential signaling driving unit, said transmission minimized differential signaling driving unit stopping the signal conversion mode in response to said first level of the clock detecting signal; and   said clock signal detecting unit outputting the second level of the clock detecting signal to the transmission minimized differential signaling driving unit when the transmission minimized differential signaling clock signal is input to the transmission minimized differential signaling driving unit, said transmission minimized differential signaling driving unit starting the signal conversion mode in response to said second level of the clock detecting signal.   
     
     
       26. A display apparatus having a normal power mode and a power savings mode, said apparatus comprising:
 a receiving unit for receiving a digital signal that comprises a data signal and a clock signal from an external device;   a power supply unit for supplying voltage to components of the display apparatus in the normal power mode in which the receiving unit is receiving the clock signal from the external device; and   a controller for controlling the power supply unit to convert the normal power mode to the power savings mode in response to the receiving unit being in an abnormal reception state of the clock signal from the external device,   wherein in the power savings mode, supply of the power to one or more of the components of the display apparatus is interrupted.   
     
     
       27. The display apparatus as claimed in claim 26, further comprising: a clock signal detecting unit for detecting whether the clock signal is received. 
     
     
       28. The display apparatus as claimed in claim 26, wherein the power supply unit cuts off supply of the power to the one or more components of the display unit except the controller in the power savings mode. 
     
     
       29. The display apparatus as claimed in claim 26, wherein the data signal comprises a transmission minimized differential signaling (TMDS) data signal, and the clock signal comprises a transmission minimized differential signaling (TMDS) clock signal. 
     
     
       30. The display apparatus as claimed in claim 26, further comprising:
 a display unit; and   a display driving unit for driving the display unit based on the digital signal,   wherein the controller controls the power supply unit to cut off the supply of the power to at least one of the display unit and the display driving unit in the power savings mode.   
     
     
       31. The display apparatus as claimed in claim 26, wherein the controller controls the power supply unit to convert the normal power mode to the power savings mode immediately when the abnormal reception state of the clock signal happens. 
     
     
       32. The display apparatus as claimed in claim 26, wherein the abnormal reception state of the clock signal comprises a state in which the clock signal is not received by the receiving unit from the external device. 
     
     
       33. The display apparatus as claimed in claim 26, wherein the abnormal reception state of the clock signal comprises a state in which the external device is not connected to the receiving unit. 
     
     
       34. The display apparatus as claimed in claim 26,
 wherein the receiving unit comprises a port configured to be connected with a connector of the external device to receive the digital signal, and   wherein the abnormal reception state of the clock signal comprises a state in which the connector of the external device is disconnected from the port of the receiving unit.   
     
     
       35. The display apparatus as claimed in claim 26, wherein the abnormal reception state of the clock signal happens while the digital signal received by the receiving unit is converted to synchronous signals and a digital video signal to be output to a display driving unit. 
     
     
       36. A power saving method of a display apparatus having a normal power mode and a power savings mode, the method comprising:
 receiving a digital signal comprising a data signal and a clock signal in the normal power mode from an external device;   supplying power to components of the display apparatus in the normal power mode in which the clock signal is being received from the external device;   converting the normal power mode to the power savings mode in response to the display apparatus being in an abnormal reception state of the clock signal,   wherein in the power savings mode, supply of the power to one or more of the components of the display apparatus is interrupted.   
     
     
       37. The power saving method as claimed in claim 36, wherein the converting step comprises partly cutting off the supply of the voltage to the one or more of the components of the display apparatus in the power savings mode. 
     
     
       38. The power saving method as claimed in claim 36, wherein the data signal comprises a transmission minimized differential signaling (TMDS) data signal, and the clock signal comprises a transmission minimized differential signaling (TMDS) clock signal. 
     
     
       39. The power saving method as claimed in claim 36, wherein the converting the normal power mode to the power savings mode immediately when the abnormal reception state of the clock signal happens. 
     
     
       40. The power saving method as claimed in claim 36, wherein the abnormal reception state of the clock signal comprises a state in which the clock signal is not received from the external device. 
     
     
       41. The power saving method as claimed in claim 36, wherein the abnormal reception state of the clock signal comprises a state in which the external device is not connected to the display apparatus. 
     
     
       42. The power saving method as claimed in claim 36, wherein the abnormal reception state of the clock signal happens while the received digital signal is converted to synchronous signals and a digital video signal to be output to drive a display unit of the display apparatus. 
     
     
       43. A display apparatus having a normal power mode and a power savings mode, said apparatus comprising:
 a receiving unit for receiving a digital signal that comprises a data signal and a clock signal from an external device;   a power supply unit for supplying power to components of the display apparatus; and   a controller for controlling the power supply unit to supply the power to the components of the display apparatus in the normal power mode in which the clock signal is being received by the receiving unit from the external device, and to convert the normal power mode to the power savings mode in response to the clock signal not being received by the receiving unit;   wherein in the power savings mode, supply of the power to one or more of the components of the display apparatus is interrupted.   
     
     
       44. The display apparatus as claimed in claim 43, further comprising:
 a clock signal detecting unit for detecting whether the clock signal is received.   
     
     
       45. The display apparatus as claimed in claim 43, wherein the power supply unit cuts off the supply of the power to the one or more of the components of the display apparatus except the controller in the power savings mode. 
     
     
       46. The display apparatus as claimed in claim 43, wherein the data signal comprises a transmission minimized differential signaling (TMDS) data signal, and the clock signal comprises a transmission minimized differential signaling (TMDS) clock signal. 
     
     
       47. The display apparatus as claimed in claim 43, further comprising:
 a display unit; and   a display driving unit for driving the display unit based on the digital signal,   wherein the controller controls the power supply unit to cut off the supply of the power to at least one of the display unit and the display driving unit in the power savings mode.   
     
     
       48. A display apparatus comprising:
 a display unit;   a driver configured to convert a transmission minimized differential signaling (TMDS) data signal and a TMDS clock signal input to the driver into a video signal and a synchronous signal to display an image on the display unit; and   a power supply configured to supply power to the display unit if the driver is receiving the TMDS clock signal from an external device and reduce the power supplied to the display unit in response to the driver being in an abnormal reception state of the TMDS clock signal.   
     
     
       49. The display apparatus as claimed in claim 48, wherein the power supply cuts off the power supplied to the display unit in response to the driver being in the abnormal reception state of the TMDS clock signal. 
     
     
       50. The display apparatus as claimed in claim 48, further comprising a controller configured to control the power supply to supply the power to the display unit. 
     
     
       51. The display apparatus as claimed in claim 50,
 wherein the controller outputs a power-down signal to the driver in response to the driver being in the abnormal reception state of the TMDS clock signal, and   wherein, in response to receiving the power-down signal, the driver stops an operation for converting the TMDS data signal and the TMDS clock signal.   
     
     
       52. The display apparatus as claimed in claim 51,
 wherein the controller outputs a restoring signal to the driver after the driver being out of the abnormal reception state of the TMDS clock signal, and   wherein, in response to receiving the restoring signal, the driver restores the operation for converting the TMDS data signal and the TMDS clock signal.   
     
     
       53. The display apparatus as claimed in claim 50,
 wherein the controller outputs a restoring signal to the power supply after the driver being out of the abnormal reception state of the TMDS clock signal, and   wherein, in response to receiving the restoring signal, the power supply restores the power supplied to the display unit.   
     
     
       54. The display apparatus as claimed in claim 48, wherein in response to the driver being in the abnormal reception state of the TMDS clock signal, the driver stops an operation for converting the TMDS data signal and the TMDS clock signal. 
     
     
       55. The display apparatus as claimed in claim 54, wherein after the driver being out of the abnormal reception state of the TMDS clock signal, the driver restores the operation for converting the TMDS data signal and the TMDS clock signal. 
     
     
       56. The display apparatus as claimed in claim 48, wherein after the driver being out of the abnormal reception state of the TMDS clock signal, the power supply restores the power supplied to the display unit. 
     
     
       57. The display apparatus as claimed in claim 48, wherein the driver comprises:
 a capacitor configured to remove a direct current component of the TMDS clock signal; and   at least one transistor configured to be switched based on the TMDS clock signal, from which the direct current component has been removed, to output an output signal to control the power supply.   
     
     
       58. The display apparatus as claimed in claim 48, further comprising a display driver configured to drive the display based on the video signal and the synchronous signal output by the driver. 
     
     
       59. The display apparatus as claimed in claim 48, wherein the power supply is configured to reduce the power supplied to the display unit immediately when the driver is in the abnormal reception state of the TMDS clock signal happens. 
     
     
       60. The display apparatus as claimed in claim 48, wherein the abnormal reception state of the TMDS clock signal comprises a state in which the TMDS clock signal is not received by the driver from the external device. 
     
     
       61. The display apparatus as claimed in claim 48, wherein the abnormal reception state of the TMDS clock signal comprises a state in which the external device is not connected to the driver. 
     
     
       62. The display apparatus as claimed in claim 48, further comprising:
 a display driver configured to drive the display unit of the display apparatus based on the video signal and the synchronous signal output by the driver.   
     
     
       63. A display apparatus comprising:
 a display unit;   a transmission minimized differential signaling (TMDS) driving unit configured to receive a TMDS data signal and a TMDS clock signal for displaying the image on the display unit; and   a controller configured to control power supplied to the display unit if the TMDS driving unit is receiving the TMDS clock signal from an external device and reduce the power supplied to the display unit in response to the TMDS driving unit being in an abnormal reception state of the TMDS clock signal.   
     
     
       64. The display apparatus as claimed in claim 63, wherein the TMDS driving unit is configured to convert the TMDS data signal and the TMDS clock signal input to the TMDS driving unit into a video signal and a synchronous signal. 
     
     
       65. The display apparatus as claimed in claim 63, wherein the TMDS driving unit comprises a clock signal input configured to input the TMDS clock signal. 
     
     
       66. The display apparatus as claimed in claim 63, wherein the abnormal reception state of the TMDS clock signal comprises a state in which the TMDS clock signal is not received by the TMDS driving unit. 
     
     
       67. The display apparatus as claimed in claim 63, wherein the controller is configured to reduce the power supplied to the display unit immediately when the TMDS driving unit is in an abnormal reception state of the TMDS clock signal. 
     
     
       68. A display apparatus comprising:
 a display unit;   a transmission minimized differential signaling (TMDS) driving unit configured to receive a TMDS data signal and a TMDS clock signal for displaying the image on the display unit; and   a controller configured to control power supplied to the display unit if the TMDS driving unit is receiving the TMDS clock signal from an external device and, in response to the TMDS clock signal not being input to the TMDS driving unit, control the display apparatus to be set as a power-saving mode and output a power down signal to reduce the power supplied to the display unit.   
     
     
       69. The display apparatus as claimed in claim 68, wherein the TMDS driving unit is configured to convert a TMDS data signal and a TMDS clock signal input to the TMDS driving unit into a video signal and a synchronous signal. 
     
     
       70. The display apparatus as claimed in claim 69, wherein the TMDS driving unit comprises a clock signal input configured to input the TMDS clock signal. 
     
     
       71. The display apparatus as claimed in claim 70, wherein the abnormal reception state of the TMDS clock signal comprises a state in which the TMDS clock signal is not received by the TMDS driving unit. 
     
     
       72. The display apparatus as claimed in claim 68, wherein the controller is configured to control the display apparatus to be set as a power-saving mode and output a power down signal to reduce the power supplied to the display unit, immediately when the TMDS clock signal is not input to the TMDS driving unit. 
     
     
       73. A display apparatus comprising:
 a display unit;   a driver configured to receive a transmission minimized differential signaling (TMDS) data signal and a TMDS clock signal and output a video signal and a synchronous signal to display an image on the display unit based on the received TMDS data signal and the received TMDS clock signal; and   a power supply configured to supply power to the display unit if the driver is in a first state in which the driver is outputting the video signal and the synchronous signal based on the received TMDS data signal and the received TMDS clock signal, and reduce the power supplied to the display unit if the driver is in a second state in which the driver is not outputting the video signal and the synchronous signal in response to an interrupted state of the TMDS data signal and the TMDS clock signal.   
     
     
       74. The display apparatus as claimed in claim 73, wherein the power supply reduces the power supplied to the display unit immediately when the driver is in the second state. 
     
     
       75. The display apparatus as claimed in claim 73, wherein the interrupted state of the TMDS data signal and the TMDS clock signal comprises a state in which the TMDS clock signal is not received by the driver from an external device. 
     
     
       76. The display apparatus as claimed in claim 73, wherein the interrupted state of the TMDS data signal and the TMDS clock signal comprises a state in which the external device is not connected to the driver. 
     
     
       77. The display apparatus as claimed in claim 73,
 wherein the driver comprises a port configured to be connected with a connector of the external device to receive the TMDS data signal and the TMDS clock signal, and   wherein the interrupted state of the TMDS data signal and the TMDS clock signal comprises a state in which the connector of the external device is disconnected from the port of the driver.   
     
     
       78. The display apparatus as claimed in claim 73, wherein the interrupted state of the TMDS data signal and the TMDS clock signal happens while driver is being in the first state. 
     
     
       79. A display apparatus comprising:
 a display unit;   a transmission minimized differential signaling (TMDS) driving unit configured to receive a TMDS signal for displaying an image on the display unit;   a power supply configured to supply power to the display unit; and   a controller configured to reduce the power supplied to the display unit in response to the TMDS signal not being input to the TMDS driving unit,   wherein the TMDS signal comprises a TMDS data signal and a TMDS clock signal.   
     
     
       80. The display apparatus as claimed in claim 79, wherein the power supply cuts off the power supplied to the display unit in response to the TMDS signal not being input to the TMDS driving unit. 
     
     
       81. The display apparatus as claimed in claim 79, wherein the TMDS driving unit is configured to convert the TMDS signal into a video signal and a synchronous signal. 
     
     
       82. A display apparatus comprising:
 a display;   a transmission minimized differential signaling (TMDS) driving unit configured to receive a TMDS data signal and a TMDS clock signal for displaying an image on the display; and   a controller configured to change a first state of the display into a second state of the display based on whether the TMDS clock signal is input to the TMDS driving unit or not.   
     
     
       83. The display apparatus as claimed in claim 82,
 wherein the first state and the second state of the display comprise power supply states of the display, and   wherein a level of power which is supplied to the display in the second state is less than a level of power which is supplied to the display in the first state.   
     
     
       84. The display apparatus as claimed in claim 82, wherein the controller is configured to change the first state of the display into the second state of the display immediately when the TMDS clock signal is not input to the TMDS driving unit. 
     
     
       85. A method of controlling a display apparatus, the method comprising:
 determining whether a transmission minimized differential signaling (TMDS) clock signal is input to a TMDS driving unit of the display apparatus, the TMDS clock signal being input together with a TMDS data signal for displaying an image on the display apparatus; and   changing a first state of the display apparatus into a second state of the display apparatus according that the TMDS clock signal is input to the display apparatus.   
     
     
       86. The method as claimed in claim 85,
 wherein, the first state and the second state of the display apparatus comprise power supply states of the display apparatus, and   wherein, a level of power which is supplied to the display apparatus in the second state is less than a level of power which is supplied to the display apparatus in the first state.   
     
     
       87. The method as claimed in claim 85, wherein the changing comprises changing the first state of the display apparatus into the second state of the display apparatus immediately when the TMDS clock signal is not input to the TMDS driving unit of the display apparatus.