Semiconductor device, semiconductor memory device and data processing system comprising semiconductor system

Abstract

A semiconductor device comprises a memory cell, a bit line, a sense amplifier operating between a first voltage and a second voltage higher than the first voltage, a transfer control circuit including a transfer transistor, and a write circuit writing data into the memory cell through the bit line based on the first voltage and a third voltage. The sense amplifier receives and amplifiers the signal voltage at a sense node when the transfer transistor controls the connection between the bit line and the sense node in response to a transfer control voltage. The third voltage is set to a voltage lower than the second voltage and higher than the transfer control voltage, and the sense node is set to a voltage higher than the transfer control voltage in an initial period of a read operation before the data of the memory cell is read out to the bit line.

The invention claimed is: 
     
       1. A semiconductor device comprising:
 a memory cell storing data; 
 a bit line connected to the memory cell; 
 a sense amplifier operating between a first voltage and a second voltage higher than the first voltage, the sense amplifier receiving a signal voltage read out to the bit line in response to the data of the memory cell at a sense node connected to a gate of a transistor and amplifying a voltage at the sense node; 
 a transfer control circuit including a transfer transistor controlling an electrical connection between the bit line and the sense node in response to a transfer control voltage inputted to a gate; and 
 a write circuit writing data into the memory cell through the bit line based on the first voltage and a third voltage corresponding to data of high-level of the memory cell, 
 wherein the third voltage is set to a voltage lower than the second voltage and higher than the transfer control voltage, 
 and the sense node is set to a voltage higher than the transfer control voltage in an initial period of a read operation before the data of the memory cell is read out to the bit line. 
 
     
     
       2. The semiconductor device according to  claim 1 , wherein a reference voltage of the bit line set in the initial period of the read operation is lower than the transfer control voltage by a threshold voltage of the transfer transistor. 
     
     
       3. The semiconductor device according to  claim 2 , wherein the memory cell includes
 a capacitor storing data corresponding to stored charge and 
 a select transistor connected between one electrode of the capacitor and the bit line, the select transistor having a gate connected to a word line. 
 
     
     
       4. The semiconductor device according to  claim 3 , wherein a P-N junction portion is formed between a silicon substrate or a well on which the select transistor is formed and a drain of the select transistor connected to the one electrode of the capacitor, and the third voltage is applied to the one electrode by the write circuit. 
     
     
       5. The semiconductor device according to  claim 4 , wherein a plate voltage set to half the third voltage is applied to another electrode of the capacitor. 
     
     
       6. The semiconductor device according to  claim 1 ,
 wherein the sense amplifier is a single-ended amplifier, 
 and a first transistor having a gate connected to the sense node and a second transistor having a gate to which a sensing period control signal is applied are connected in series between an input/output node of the sense amplifier and a first power supply line receiving the first voltage. 
 
     
     
       7. The semiconductor device according to  claim 6 , wherein the input/output node is connected to an input side of the write circuit, the signal voltage amplified by the sense amplifier is transmitted to the write circuit via the input/output node, and the write circuit restores the data into the memory cell using the third voltage. 
     
     
       8. The semiconductor device according to  claim 7 , wherein the sense amplifier includes a sense amplifier input/output latch latching the signal voltage of the input/output node. 
     
     
       9. The semiconductor device according to  claim 1 , wherein the sense node is set to a voltage higher than the second voltage in the initial period of the read operation. 
     
     
       10. A semiconductor memory device comprising:
 a memory cell storing data in response to stored charge; 
 a bit line connected to the memory cell; 
 a transfer control circuit controlling an electrical connection between the bit line and a sense node based on a relation between a reference voltage set for the bit line before the memory cell is connected to the bit line and a voltage of the bit line shifted from the reference voltage when the memory cell is connected to the bit line; 
 a sense amplifier having a single ended configuration in which the sense node is connected to a gate of a transistor, the sense amplifier amplifying a signal voltage at the sense node; and 
 a write circuit writing data into the memory cell through the bit line based on a write voltage corresponding to data of high-level of the memory cell, 
 wherein the write voltage is set lower than an operation voltage of the sense amplifier, 
 and the transfer control circuit controls so that the bit line is electrically disconnected from the sense node when the voltage of the bit line shifted from the reference voltage is higher than the reference voltage, and the bit line is electrically connected to the sense node when the voltage of the bit line is lower than the reference voltage, in a state in which a voltage at the sense node is set to the operation voltage of the sense amplifier. 
 
     
     
       11. The semiconductor memory device according to  claim 10 , wherein the reference voltage is set lower than the write voltage and higher than a voltage corresponding to low-level data of the memory cell. 
     
     
       12. The semiconductor memory device according to  claim 10 , wherein the transfer control circuit includes a transfer transistor controlling an electrical connection between the bit line and the sense node in response to a transfer control voltage inputted to a gate of the transfer transistor. 
     
     
       13. The semiconductor memory device according to  claim 12 , wherein the write voltage is higher than the transfer control voltage. 
     
     
       14. The semiconductor memory device according to  claim 12 , wherein the reference voltage is lower than the transfer control voltage by a threshold voltage of the transfer transistor. 
     
     
       15. The semiconductor memory device according to  claim 10 , wherein the memory cell includes a capacitor and a select transistor connected between one electrode of the capacitor and the bit line, the select transistor having a gate connected to a word line. 
     
     
       16. The semiconductor memory device according to  claim 15 , wherein a P-N junction portion is formed between a silicon substrate or a well on which the select transistor is formed and a drain of the select transistor connected to the one electrode of the capacitor, and the third voltage is applied to the one electrode by the write circuit. 
     
     
       17. The semiconductor memory device according to  claim 16 , wherein a plate voltage set to half the write voltage is applied to another electrode of the capacitor. 
     
     
       18. A data processing system comprising:
 a semiconductor device; and 
 a controller connected to the semiconductor device through a bus, the controller processing data stored in the semiconductor device and controlling an operation of the system as a whole and an operation of the semiconductor device, 
 the semiconductor device comprising: 
 a memory cell storing data; 
 a bit line connected to the memory cell; 
 a sense amplifier operating between a first voltage and a second voltage higher than the first voltage, the sense amplifier receiving a signal voltage read out to the bit line in response to the data of the memory cell at a sense node connected to a gate of a transistor and amplifying a voltage at the sense node; 
 a transfer control circuit including a transfer transistor controlling an electrical connection between the bit line and the sense node in response to a transfer control voltage inputted to a gate; 
 a write circuit writing data into the memory cell through the bit line based on a write voltage corresponding to data of high-level of the memory cell; and 
 an interface communicating through the bus, 
 wherein the third voltage is set to a voltage lower than the second voltage and higher than the transfer control voltage, 
 and the sense node is set to a voltage higher than the transfer control voltage in an initial period of a read operation before the data of the memory cell is read out to the bit line. 
 
     
     
       19. The data processing system according to  claim 18 , wherein a reference voltage of the bit line set in the initial period of the read operation is lower than the transfer control voltage by a threshold voltage of the transfer transistor. 
     
     
       20. The data processing system according to  claim 19 , wherein the controller includes
 a command issuing circuit sending commands to the semiconductor device through the bus, 
 and a data processing circuit sending and receiving data to and from the semiconductor device through the bus to perform processes required for the controlling. 
 
     
     
       21. A method for reading data in a dynamic random access memory comprising:
 precharging a bit line to a ground potential;   precharging a sense node to a sense node precharge voltage;   applying a transfer control voltage to a gate of a transfer transistor connected between the sense node and the bit line to charge the bit line to a reference voltage;   driving a word line connected to a gate of a select transistor of a memory cell to a word line supply voltage to connect a capacitor of the memory cell to the bit line;   activating a single-ended sense amplifier having an input connected to the sense node to read data in the memory cell; and   activating a write circuit having an input connected to an output of the sense amplifier and an output connected to the bit line to restore the data to the memory cell;   wherein the reference voltage has a value lower than the transfer control voltage by a threshold voltage of the transfer transistor.    
     
     
       22. The method as claimed in claim 21, wherein the write circuit restores a ground potential to the memory cell when the sense amplifier reads low level data in the memory cell and restores a voltage less than the sense node precharge voltage when the sense amplifier reads high level data in the memory cell.  
     
     
       23. The method as claimed in claim 22, wherein the voltage less than the sense node precharge voltage is one half the sense node precharge voltage.  
     
     
       24. The method as claimed in claim 22, wherein the transfer control voltage is less than the voltage less than the sense node precharge voltage.  
     
     
       25. The method as claimed in claim 22, wherein the write circuit comprises:
 an inverter circuit driven by the voltage less than the sense node precharge voltage and the ground potential and having an input connected to the output of the sense amplifier; and   a transistor connected between the output of the inverter and the bit line and having a gate connected to a write control signal.    
     
     
       26. The method as claimed in claim 25, wherein the inverter comprises:
 a PMOS transistor connected between the voltage less than the sense node precharge voltage and the output of the inverter; and   an NMOS transistor connected between the ground potential and the output of the inverter; wherein each of the PMOS transistor and the NMOS transistor comprises a gate connected to the output of the sense amplifier.    
     
     
       27. The method as claimed in claim 21, wherein the sense amplifier is powered by the sense node precharge voltage.  
     
     
       28. The method as claimed in claim 21, wherein the sense node precharge voltage is higher than the voltage powering the sense amplifier.  
     
     
       29. The method as claimed in claim 21, wherein the transfer control voltage is less than the sense node precharge voltage.  
     
     
       30. The method as claimed in claim 21, wherein the sense amplifier is powered by a voltage equal to the voltage to which the word line is driven.  
     
     
       31. The method as claimed in claim 21, wherein the sense node is precharged through a PMOS transistor connected between the sense node and the sense node precharge voltage.  
     
     
       32. The method as claimed in claim 21, wherein the sense amplifier comprises a cross coupled pair of CMOS inverters.  
     
     
       33. The method as claimed in claim 32, wherein the sense amplifier comprises a detection transistor connected between the cross coupled pair of CMOS inverters and the ground potential and having a gate connected to the sense node.  
     
     
       34. The method as claimed in claim 32, wherein the sense amplifier comprises a precharge transistor connected between the cross coupled pair of CMOS inverters and a voltage source.