PMOS depletable drain extension made from NMOS dual depletable drain extensions

Abstract

In accordance with an embodiment of the invention, there is an integrated circuit device having a complementary integrated circuit structure comprising a first MOS device. The first MOS device comprises a source doped to a first conductivity type, a drain extension doped to the first conductivity type separated from the source by a gate, and an extension region doped to a second conductivity type underlying at least a portion of the drain extension adjacent to the gate. The integrated circuit structure also comprises a second complementary MOS device comprising a dual drain extension structure.

What is claimed is: 
     
       1. A complementary integrated circuit structure comprising:
 a first MOS device comprising,
 a first gate; 
 a source doped to a first conductivity type; 
 a drain extension doped to the first conductivity type separated from the source by the first gate; 
 a drain contact doped to the first conductivity type; and 
 an extension region doped to a second conductivity type underlying at least a portion of the drain extension adjacent to the first gate; 
   a second complementary MOS device comprising,
 a second gate; 
 a dual drain extension structure; and 
   an island doped to the first conductivity type underlying the first gate and the second gate,   wherein,   the drain contact of the first MOS device contacts the island; and   the first conductivity type is one of N-type and P-type, and the second conductivity type is the other one of N-type and P-type.   
     
     
       2. The complementary integrated circuit structure according to  claim 1 , wherein the drain extension in the first MOS device is formed from a layer that forms a drain extension in the second complementary MOS device. 
     
     
       3. The complementary integrated circuit structure according to  claim 1 , wherein the extension region in the first MOS device is formed from a layer that forms an extension region in the second complementary MOS device. 
     
     
       4. The complementary integrated circuit structure according to  claim 1  wherein first MOS device further comprises:
 a body contact contacting the extension region and doped to the second conductivity type; and 
 the drain contact further contacts the drain extension. 
 
     
     
       5. The complementary integrated circuit structure according to  claim 1  further comprising:
 a field region disposed adjacent to the drain extension. 
 
     
     
       6. The complementary integrated circuit structure according to  claim 1 , wherein the drain extension has a net doping concentration of about 5E11 ions/cm 2  to about 1.5E12 ions/cm 2 . 
     
     
       7. The complementary integrated circuit structure according to  claim 1 , wherein the extension region has a net doping concentration of about 1E12 ions/cm 2  to about 3E12 ions/cm 2 . 
     
     
       8. The complementary integrated circuit structure according to  claim 1  further comprising:
 a link layer doped to the first conductivity type contacting the drain extension and a channel disposed under the gate, wherein the link layer has a higher dopant concentration than the drain extension. 
 
     
     
       9. The complementary integrated circuit structure according to  claim 1  further comprising:
 a well doped to the second conductivity type surrounding the source. 
 
     
     
       10. The complementary integrated circuit structure according to  claim 8 , wherein the link layer has a length of about 0.5 μm to about 5.0 μm. 
     
     
       11. The complementary integrated circuit structure according to  claim 1  wherein the extension region surrounds the drain extension. 
     
     
       12. A complementary integrated circuit structure comprising:
 a first MOS device comprising,
 a first gate; 
 a first source doped to a first conductivity type; 
 a drain contact doped to the first conductivity type; and 
 a single drain extension separated from the first source by a first gate; and 
   a second complementary MOS device comprising;
 a second gate; 
 a second source doped to a second conductivity type; 
 a dual drain extension separated from the second source by a second gate, 
   an island doped to the first conductivity type underlying the first gate and the second gate,   wherein the first conductivity type is one of N-type and P-type, and the second conductivity type is the other one of N-type and P-type.   
     
     
       13. The complementary integrated circuit structure according to  claim 12 , wherein the single drain extension comprises a layer that is also used in the dual drain extension. 
     
     
       14. The complementary integrated circuit structure according to  claim 12 , wherein the single drain extension totally depletes at a reverse drain to body bias before breakdown occurs at a drain extension to body junction under an edge of the first gate. 
     
     
       15. The complementary integrated circuit structure according to  claim 12 , further comprising:
 a link layer doped to the first conductivity type contacting the single drain extension and a first channel disposed under the first gate, wherein the link layer has a higher dopant concentration than the drain extension.   
     
     
       16. The complementary integrated circuit structure according to  claim 15 , wherein the single drain extension totally depletes at a drain to body reverse bias below that at which a link layer to body junction under an edge of the first gate breaks down. 
     
     
       17. The complementary integrated circuit structure according to  claim 12 , wherein the first source is disposed in a first well doped to the second conductivity type. 
     
     
       18. The complementary integrated circuit structure according to  claim 12 , wherein the first MOS device and the second complementary MOS device have a breakdown voltage greater than about 50V. 
     
     
       19. The complementary integrated circuit structure according to  claim 17 , wherein a portion of the single drain extension is disposed in the first well. 
     
     
       20. An integrated circuit structure comprising:
 a first MOS device comprising,
 a first gate; 
 a first source doped to a first conductivity type; 
 a first drain extension formed in a first layer, the first drain extension doped to the first conductivity type and separated from the first source by at least a portion of the first gate; and 
 a first well region formed in a second layer underlying the first source and at least a portion of the first drain extension, the first well region doped to a second conductivity type; and 
   the first MOS device further comprising a drain contact doped to the first conductivity type and formed at least partially in the first well region and overlapping at least a portion of the first drain extension; and
 at least a second MOS device comprising either a first region made from the first layer or a second region made from the second layer.  
   
     
     
       21. The integrated circuit structure of claim 20, wherein the drain contact is formed entirely within the first well region.  
     
     
       22. The integrated circuit structure of claim 20, wherein the first drain extension is formed entirely within the first well region.  
     
     
       23. The integrated circuit structure of claim 20, wherein a portion of the drain contact is formed outside the first drain extension.  
     
     
       24. The integrated circuit structure of claim 20, wherein the first well region is formed within a third layer doped to the first conductivity type.  
     
     
       25. The integrated circuit structure of claim 24, wherein at least a portion of the first well region between the first drain extension and the third layer depletes at a first drain to a first well voltage below a breakdown voltage of the first MOS device.  
     
     
       26. The integrated circuit structure of claim 25, wherein a portion of the first well region doped to the second conductivity type between the first drain extension doped to the first conductivity type and the third layer doped to the first conductivity type depletes due to a combined extension of depletion layers into opposite sides of the first well region from at least one PN junction between the first drain extension and first well region and between the third region and first well region. 
     
     
       27. The integrated circuit structure of claim 26, wherein the first drain extension depletes at the first drain to a first well bias voltage less than a breakdown voltage of the first MOS device.  
     
     
       28. The integrated circuit structure of claim 20, further comprising a first link region doped to the first conductivity type adjacent to the first gate at a first edge and abutting the first drain extension at an opposite edge.  
     
     
       29. The integrated circuit structure of claim 20, further comprising a second well region doped to the second conductivity type below at least the first source and the first gate.  
     
     
       30. The integrated circuit structure of claim 20, wherein the at least a second MOS device comprises a first region made from the first layer and a second region made from the second layer.