Semiconductor memory device

Abstract

A semiconductor memory device which can reduce the size of a memory cell and increase the packing density is disclosed. Each memory cell comprises a p-type active region, an n-type active region, two word lines, a common gate line and a common gate line. Two memory cells are deviated by, for example, an amount of a half bit in the direction which perpendicularly crosses the word line direction. The memory cells are arranged with one of their parts overlapped with one another in the word line direction. Thus, the size of the memory cell can be reduced in the word line direction.

What is claimed is: 
     
       1. A semiconductor memory device having a plurality of SRAM cells each comprising a first transistor of a first conductive type and a second transistor of a second conductive type,
 wherein a first active region in which a channel of the first transistor is formed and a second active region in which a channel of the second transistor is formed are arranged so that the channel current direction of the first transistor and the channel current direction of the second transistor are in parallel to each other in each memory cell, and 
 two memory cells, among the plurality of memory cells, which are adjacent to each other in one direction which perpendicularly crosses the channel current direction have a positional relation such that the two memory cells are deviated from each other in the channel current direction. 
 
     
     
       2. The semiconductor memory device according to  claim 1 , wherein two memory cells, among the plurality of memory cells, which are adjacent to each other in the other direction which perpendicularly crosses the channel current direction have a positional relation such that the two memory cells are aligned in the channel current direction. 
     
     
       3. A semiconductor memory device having a plurality of SRAM cells each comprising a first transistor of a first conductive type and a second transistor of a second conductive type,
 wherein a first active region in which a channel of the first transistor is formed and a second active region in which a channel of the second transistor is formed are arranged so that the channel current direction of the first transistor and the channel current direction of the second transistor are in parallel to each other in each memory cell, and 
 two memory cells, among the plurality of memory cells, which are adjacent to each other in one direction which perpendicularly crosses the channel current direction have a positional relation such that the two memory cells are deviated from each other in the channel current direction and a part of a memory cell region of one of the two memory cells is overlapped with a part of a memory cell region of the other memory cell. 
 
     
     
       4. The semiconductor memory device according to  claim 3 , wherein two memory cells, among the plurality of memory cells, which are adjacent to each other in the other direction which perpendicularly crosses the channel current direction have a positional relation such that the two memory cells are aligned in the channel current direction. 
     
     
       5. The semiconductor memory device according to  claim 3 , wherein the first and second active regions are isolated from each other between the adjacent two memory cells. 
     
     
       6. The semiconductor memory device according to  claim 3 , wherein a pattern of a wiring layer which also serves as gate electrodes of the first and second transistors is disposed so as to perpendicularly cross the first or the second active region on the first or second active region. 
     
     
       7. The semiconductor memory device according to  claim 3 , wherein four of the first transistors are provided in series in the first active region, and
 two of the second transistors are provided in series in the second active region. 
 
     
     
       8. The semiconductor memory device according to  claim 7 , wherein each memory cell comprises:
 stripe-shaped two word lines arranged in parallel, each of which is arranged so as to perpendicularly cross the first active region and also serves as a gate electrode of a word transistor of the first conductive type; and 
 two common gate lines which are arranged in parallel to each other, each of which perpendicularly crosses both of the first and second active regions and connects gates of a set of a driving transistor of the first conductive type and a load transistor of the second conductive type. 
 
     
     
       9. A semiconductor memory device having a plurality of SRAM cells each comprising:
 a word transistor of a first conductive type, a drive transistor of the first conductivity type and a load transistor of a second conductive type,   wherein a first active region in which a channel of the word transistor and a channel of the drive transistor are formed and a second active region in which a channel of the load transistor is formed are arranged so that the channel current direction of the word transistor, the channel current direction of the drive transistor and the channel current direction of the load transistor are in parallel to each other in each of the SRAM cells, and   wherein two SRAM cells, among the plurality of SRAM cells, which are adjacent to each other in one direction which perpendicularly crosses the channel current direction have a positional relation such that the two SRAM cells are deviated from each other in the channel current direction.    
     
     
       10. The semiconductor memory device according to claim 9, wherein one of the two SRAM cells is between a first adjacent SRAM cell and a second adjacent SRAM cell.  
     
     
       11. The semiconductor memory device according to claim 10, wherein the first and second adjacent SRAM cells and said one of the two SRAM cells are disposed along a direction that is perpendicular to the channel current direction.  
     
     
       12. The semiconductor memory device according to claim 10, wherein the first active region and the second active region are in said one of the two SRAM cells, the first active region and the second active region being isolated from active regions in the first adjacent SRAM cell and active regions in the second adjacent SRAM cell.  
     
     
       13. The semiconductor memory device according to claim 10, wherein a local word line is a gate electrode of the word transistor in said one of the two SRAM cells and a gate electrode of another word transistor in the second adjacent SRAM cell.  
     
     
       14. The semiconductor memory device according to claim 9, wherein a common gate line is a gate electrode of the drive transistor and a gate electrode of the load transistor, the common gate line perpendicularly crossing the first active region and the second active region.  
     
     
       15. The semiconductor memory device according to claim 9, wherein gate electrodes of the word transistors in the two SRAM cells are electrically connected to a common word line.  
     
     
       16. The semiconductor memory device according to claim 9, wherein the first conductivity type is n-type and the second conductivity type is p-type.