Programming memory with reduced pass voltage disturb and floating gate-to-control gate leakage

Abstract

Program disturb is reduced in a non-volatile storage system by programming storage elements on a selected word line WLn in separate groups, according to the state of their WLn−1 neighbor storage element, and applying an optimal pass voltage to WLn−1 for each group. Initially, the states of the storage elements on WLn−1 are read. A program iteration includes multiple program pulses. A first program pulse is applied to WLn while a first pass voltage is applied to WLn−1, a first group of WLn storage elements is selected for programming, and a second group of WLn storage elements is inhibited. Next, a second program pulse is applied to WLn while a second pass voltage is applied to WLn−1, the second first group of WLn storage elements is selected for programming, and the first group of WLn storage elements is inhibited. A group can include one or more data states.

What is claimed is: 
     
       1. A method for operating a non-volatile storage system which includes a set of non-volatile storage elements in communication with a set of word lines and a set of bit lines, the method comprising:
 performing at least one sense operation involving an adjacent word line of a selected word line of the set of word lines, the at least one sense operation demarcates M≧2 groups of non-volatile storage elements on the adjacent word line, the groups of non-volatile storage elements are associated with M≧2 corresponding groups of bit lines of the set of bit lines, including at least first and second groups of bit lines; and 
 performing multiple iterations of a programming sequence, including at least one iteration which includes:
 applying a first programming pulse to the selected word line while selecting for programming, non-volatile storage elements of the selected word line which are associated with the first group of bit lines, inhibiting programming of non-volatile storage elements of the selected word line which are associated with the second group of bit lines, and applying a first pass voltage to the adjacent word line; and 
 applying a second programming pulse to the selected word line while selecting for programming, the non-volatile storage elements of the selected word line which are associated with the second group of bit lines, inhibiting programming of the non-volatile storage elements of the selected word line which are associated with the first group of bit lines, and applying a second pass voltage to the adjacent word line. 
 
 
     
     
       2. The method of  claim 1 , wherein no verify operation is performed for non-volatile storage elements of the selected word line between the first and second programming pulses of the at least one iteration, the method further comprising:
 after the second programming pulse, performing a verifying operation for non-volatile storage elements of the selected word line, after which another iteration of the programming sequence is performed. 
 
     
     
       3. The method of  claim 1 , wherein:
 the non-volatile storage elements on the adjacent word line store data in at least M+1 data states; and 
 the at least one sense operation demarcates only M≧2 groups of non-volatile storage elements on the adjacent word line. 
 
     
     
       4. The method of  claim 1 , wherein:
 the at least one sense operation demarcates the M≧2 groups of non-volatile storage elements on the adjacent word line according to threshold voltages of the non-volatile storage elements on the adjacent word line; 
 non-volatile storage elements of the adjacent word line which are associated with the first group of bit lines have lower threshold voltages than non-volatile storage elements of the adjacent word line which are associated with the second group of bit lines; and 
 the first pass voltage is lower than the second pass voltage. 
 
     
     
       5. The method of  claim 1 , wherein:
 the at least one sense operation demarcate the M≧2 groups of non-volatile storage elements on the adjacent word line according to threshold voltages of the non-volatile storage elements on the adjacent word line; 
 non-volatile storage elements of the adjacent word line which are associated with the first group of bit lines have higher threshold voltages than non-volatile storage elements of the adjacent word line which are associated with the second group of bit lines; and  
 the first pass voltage is higher than the second pass voltage. 
 
     
     
       6. The method of  claim 1 , wherein:
 at least one prior iteration of the multiple iterations of the programming sequence which occurs before the at least one iteration includes applying a programming pulse to the selected word line while concurrently selecting for programming, non-volatile storage elements of the selected word line which are associated with both the first and second groups of bit lines. 
 
     
     
       7. The method of  claim 6 , wherein:
 the at least one prior iteration includes applying a pass voltage to the adjacent word line whose amplitude is between amplitudes of the first and second pass voltages. 
 
     
     
       8. The method of  claim 1 , wherein:
 the adjacent word line is on a source side of the selected word line. 
 
     
     
       9. The method of  claim 1 , wherein:
 prior iterations of the multiple iterations of the programming sequence, which occur before the at least one iteration, program at least one non-volatile storage element of the selected word line to one target data state; and 
 the at least one iteration programs at least one other non-volatile storage element of the selected word line to another target data state which is higher than the one target data state. 
 
     
     
       10. The method of  claim 9 , wherein:
 at least first and second latches are associated with one of the bit lines of the set of bit lines; 
 the at least one non-volatile storage element is programmed during the prior iterations using a first verify level, and then a second verify level which is higher than the first verify level; 
 the first latch stores a bit which indicates whether the at least one non-volatile storage element has been programmed to the first verify level; 
 the second latch stores a bit which indicates whether the at least one non-volatile storage element has been programmed to the second verify level; 
 the at least one sense operation is performed partway through the programming sequence, after the prior iterations; and 
 during the at least one sense operation, a non-volatile storage element of the adjacent word line, and associated with the one of the bit lines, is sensed, and the first latch is overwritten to store a bit to identify, at least in part, a group of the groups of non-volatile storage elements to which the non-volatile storage element of the adjacent word line belongs. 
 
     
     
       11. The method of  claim 10 , wherein:
 the at least one sense operation is performed partway through the programming sequence, after the prior iterations, in response to determining that the at least one non-volatile storage element of the selected word line has been programmed to the one target data state. 
 
     
     
       12. The method of claim 1, wherein:
 the set of non-volatile storage elements is arranged in a three-dimensional memory structure.    
     
     
       13. The method of claim 1, wherein:
 the non-volatile storage elements in the set of non-volatile storage elements comprise a non-volatile, charge storing non-conductive dielectric material.