Liquid crystal display having a reduced number of data driving circuit chips

Abstract

A liquid crystal display includes a substrate, a plurality of gate lines formed on the substrate, a plurality of data lines intersecting the plurality of gate lines, a plurality of thin film transistors connected to the plurality of gate lines and the plurality of data lines, and a plurality of pixel electrodes connected to the plurality of thin film transistors and arranged in a matrix, wherein each of the pixel electrodes includes a first side parallel to each gate line and a second side being shorter than the first side, the second side being formed next to the first side, wherein the plurality of pixel electrodes that are adjacent to each other in a column direction are connected to different data lines from each other.

What is claimed is: 
     
       1. A liquid crystal display comprising:
 a substrate;   a plurality of gate lines formed on the substrate and extended in a first direction;   a plurality of data lines intersecting the plurality of gate lines and extended in a second direction;   a plurality of thin film transistors connected to the plurality of gate lines and the plurality of data lines; and   a plurality of pixel electrodes connected to the plurality of thin film transistors and arranged in a matrix,   wherein each of the pixel electrodes is formed in a substantially rectangular shape elongated in the first direction and includes a first side parallel to each gate line and a second side being formed next to the first side, wherein the length of the first side is about three times longer than the length of the second side,   wherein the plurality of pixel electrodes that are adjacent to each other in the second direction are connected to different data lines from each other.   
     
     
       2. The liquid crystal display of  claim 1 , further comprising a storage electrode line, wherein at least a portion of the storage electrode line overlaps a pixel electrode. 
     
     
       3. The liquid crystal display of  claim 2 , wherein the storage electrode line extends perpendicular to a gate line. 
     
     
       4. The liquid crystal display of  claim 3 , wherein the storage electrode line is located in the same layer as a data line. 
     
     
       5. The liquid crystal display of  claim 3 , wherein the storage electrode line comprises:
 a plurality of first parts located in the same layer as the gate line and disposed between two adjacent gate lines; and   a plurality of second parts located in a different layer from the gate line, wherein the plurality of second parts intersect the gate line and connect the plurality of first parts with each other.   
     
     
       6. The liquid crystal display of  claim 5 , wherein each second part is located in the same layer as the pixel electrode. 
     
     
       7. The liquid crystal display of  claim 3 , wherein the storage electrode line includes at least one branch being adjacent to one of the plurality of gate lines and extending substantially parallel to the plurality of gate lines. 
     
     
       8. The liquid crystal display of  claim 7 , wherein a boundary of the pixel electrode is located on the at least one branch of the storage electrode line. 
     
     
       9. The liquid crystal display of  claim 2 , wherein the storage electrode line is substantially parallel to a gate line and arranged alternately with the gate line, wherein the storage electrode line is located in a same layer as the gate line. 
     
     
       10. The liquid crystal display of  claim 9 , wherein the thin film transistor comprises a drain electrode overlapping the storage electrode line. 
     
     
       11. The liquid crystal display of  claim 9 , wherein a boundary of the pixel electrode is located on the storage electrode line. 
     
     
       12. The liquid crystal display of  claim 9 , wherein the pixel electrode covers a gate line. 
     
     
       13. The liquid crystal display of  claim 9 , wherein a data line and the pixel electrode overlap each other. 
     
     
       14. The liquid crystal display of  claim 13 , further comprising an organic layer formed between the pixel electrode and the data line and between the pixel electrode and the gate line. 
     
     
       15. The liquid crystal display of  claim 1 , wherein a thin film transistor comprises:
 a gate electrode connected to a gate line; a source electrode connected to a data line; and   a drain electrode connected to a pixel electrode, wherein the source electrode and the drain electrode have a substantially bilateral symmetry.   
     
     
       16. The liquid crystal display of  claim 1 , further comprising a gate driver connected to the plurality of gate lines, wherein the gate driver comprises:
 a first gate driving circuit connected to first gate lines; and   a second gate driving circuit connected to second gate lines, wherein the first and the second gate driving circuits are located in a same layer as the plurality of gate lines, the plurality of data lines, and the plurality of thin film transistors.   
     
     
       17. The liquid crystal display of  claim 16 , wherein the first gate driving circuit and the second gate driving circuit are disposed opposite each other with respect to the substrate. 
     
     
       18. A liquid crystal display comprising:
 a substrate;   a first gate line disposed on the substrate and extended in a first direction;   a first data line crossing the first gate line and extended in a second direction;   a first thin film transistor connected to the first gate line and the first data line, respectively;   a first pixel electrode connected to the first thin film transistor and including a first side parallel to the first gate line and a second side being formed next to the first side;   a second gate line parallel to the first gate line and disposed on opposite side of the first pixel electrode to the first gate line;   a second data line parallel to the first data line and disposed on opposite side of the first pixel electrode to the first data line;   a second thin film transistor connected to the second gate line and the second data line, respectively;   a second pixel electrode connected to the second thin film transistor; and   a storage electrode line comprising a stem portion parallel to the first data line and an extending portion to the right and left from the stem portion, wherein the extending portion is parallel and adjacent to the first gate line and the second gate line,   wherein the extending portion overlaps the edge of the first pixel electrode and the edge of the second pixel electrode parallel to the first gate line,   wherein the first pixel electrode is formed in a substantially rectangular shape elongated in the first direction,   wherein the length of the first side is about three times the length of the second side,   wherein the first thin film transistor is adjacent to the first data line, and   wherein the second thin film transistor is adjacent to the second data line.   
     
     
       19. The liquid display of claim 18, wherein the first thin transistor comprises a first source electrode connected to the first date line, and
 wherein the first source electrode is disposed on the first gate line.   
     
     
       20. The liquid crystal display of claim 19, wherein the second thin transistor comprises a second source electrode connected to the second data line, and
 wherein the second source electrode is disposed on the second gate line.   
     
     
       21. The liquid crystal display of claim 20, wherein the extending portion comprises a first portion extending to the first thin film transistor and the second first thin film transistor, and a second portion extending to an opposite direction to the first portion,
 wherein a length of the first portion is shorter than a length of the second portion.   
     
     
       22. The liquid crystal display of claim 21, wherein the first thin transistor comprises a first drain electrode connected to the first pixel electrode through a first contact hole, and
 wherein the first contact hole is adjacent to an end of the first portion.   
     
     
       23. The liquid crystal display of claim 22, wherein the second thin transistor comprises a second drain electrode connected to the second pixel electrode through a second contact hole, and wherein the second contact hole is adjacent to an end of the first portion. 
     
     
       24. The liquid crystal display of claim 20, wherein the stem portion is comprises a first stem overlapping the first pixel electrode, a second stem overlapping the second pixel electrode, and a connecting portion connecting the first stem and the second stem,
 wherein the connecting portion comprises the same material as the first pixel electrode and the second electrode.   
     
     
       25. The liquid crystal display of claim 24, wherein the connecting portion connecting the first stem and the second stem through a third contact hole exposing the first stem and a fourth contact hole exposing the second stem. 
     
     
       26. The liquid crystal display of claim 18, wherein the extending portion overlaps the first side closer to the first gate line. 
     
     
       27. The liquid crystal display of claim 26, wherein the storage electrode line is disposed on the same layer as the first data line. 
     
     
       28. The liquid crystal display of claim 27, wherein the stem portion crosses the first and the second gate lines. 
     
     
       29. The liquid crystal display of claim 28, further comprising a gate driver connected to the first and the second gate lines, the gate driver comprising:
 a first gate driving circuit connected to the first gate line; and   a second gate driving circuit connected to the second gate line,   wherein the first and the second gate driving circuits are disposed on a same layer as the first and the second gate lines, the first and the second data lines, and the first and the second thin film transistors.   
     
     
       30. The liquid crystal display of claim 29, wherein the first gate driving circuit and the second gate driving circuit are disposed opposite to each other with respect to the substrate.