Operational mode control in serial-connected memory based on identifier

Abstract

Applying an adapted block isolation method to serial-connected memory components may mitigate the effects of leakage current in serial-connected non-volatile memory devices. Responsive to determining that a given memory component is not an intended destination of a command, a plurality of core components of the given memory component may be placed in a low power consumption mode, while maintaining input/output components in an active operational mode. Conveniently, aspects of the disclosed system reduce off current without adding many logic blocks into the memory devices.

What is claimed is: 
     
       1. A serial-connected memory system comprising:
 a serial-connected memory component including:
 a plurality of input components; 
 a plurality of output components; 
 a plurality of core components; 
 a control circuit adapted to, responsive to receiving a predetermined signal, place said plurality of core components into a low power consumption operational mode, while leaving said plurality of input components and said plurality of output components in an active operational mode; and 
 a comparator adapted to generate said predetermined signal responsive to determining that an identification value associated with said memory component does not match an identification value decoded from a memory component identifier present in a received command packet. 
 
 
     
     
       2. The serial-connected memory system of  claim 1  wherein said control circuit produces a core drain supply voltage. 
     
     
       3. The serial-connected memory system of  claim 2  wherein said core drain supply voltage is associated with:
 a first drain supply voltage level corresponding to a core active operational mode; and 
 a second drain supply voltage level, wherein a magnitude of said second drain supply voltage level is lesser than a magnitude of said first drain supply voltage level, said second drain supply voltage level corresponding to said low power consumption operational mode; and 
 wherein, responsive to said predetermined signal, said control circuit is adapted to reduce said core drain supply voltage from said first drain supply voltage level to said second drain supply voltage level. 
 
     
     
       4. The serial-connected memory system of  claim 1  wherein said control circuit produces a core source supply voltage. 
     
     
       5. The serial-connected memory system of  claim 4  wherein said core source supply voltage is associated with:
 a first source supply voltage level corresponding to a core active operational mode; and 
 a second source supply voltage level, wherein a magnitude of said second source supply voltage level is greater than a magnitude of said first source supply voltage level, said second source supply voltage level corresponding to said low power consumption operational mode; and 
 wherein, responsive to said predetermined signal, said control circuit is adapted to increase said core source supply voltage from said first source supply voltage level to said second source supply voltage level. 
 
     
     
       6. The serial-connected memory system of  claim 1  wherein said control circuit is adapted to reverse-bias said plurality of core components. 
     
     
       7. The serial-connected memory system of  claim 6  wherein said control circuit is adapted to reverse-bias said plurality of core components according to a gate-source reverse-biasing scheme. 
     
     
       8. The serial-connected memory system of  claim 7  wherein said control circuit is adapted to employ a gate voltage control with a fixed source voltage category of said gate-source reverse-biasing scheme. 
     
     
       9. A method of managing an operational mode of memory component in a serial-connected memory system, said method comprising:
 receiving a command, wherein said command includes a memory component identifier; 
 decoding said memory component identifier to obtain a command identification value; 
 obtaining a stored identification value associated with said memory component; 
 determining that said stored identification value does not match said command identification value; and 
 responsive to said determining, placing a plurality of core components of said memory component in a low power consumption mode. 
 
     
     
       10. The method of  claim 9  wherein said placing said plurality of core components of said memory component in a low power consumption mode comprises reducing a core drain supply voltage from a first drain supply voltage level to a second drain supply voltage level. 
     
     
       11. The method of  claim 10  wherein said reducing acts to reverse-bias a subset of said plurality of core components. 
     
     
       12. The method of  claim 11  wherein said reverse-bias is implemented according to a gate-source reverse-biasing scheme. 
     
     
       13. The method of  claim 12  wherein said reverse-bias employs a gate voltage control with a fixed source voltage category of said gate-source reverse-biasing scheme. 
     
     
       14. The method of  claim 9  wherein said placing said plurality of core components of said memory component in a low power consumption mode comprises increasing a core source supply voltage from a first source supply voltage level to a second source supply voltage level. 
     
     
       15. The method of  claim 14  wherein said increasing acts to reverse-bias a subset of said plurality of core components. 
     
     
       16. The method of  claim 15  wherein said reverse-bias is implemented according to a gate-source reverse-biasing scheme. 
     
     
       17. The method of  claim 16  wherein said reverse-bias employs a gate voltage control with a fixed source voltage category of said gate-source reverse-biasing scheme. 
     
     
       18. A system comprising:
 a controller; and   a plurality of serial-connected memory components, each of said serial connected memory components including:
 a plurality of input components; 
 a plurality of output components; 
 a plurality of core components; 
 a first control circuit configured to receive a predetermined signal, and place at least one of said plurality of core components into a first operational mode, while leaving at least one of said input components and said output components in a second operational mode; and 
 a second control circuit configured to produce said predetermined signal in response to a comparison result of an identification value associated with said memory component and an identification value associated with a memory component identifier present in a received packet. 
   
     
     
       19. The system of claim 18 wherein each of said serial-connected memory components further includes a comparator configured to compare the identification value associated with said memory component to the identification value associated with the memory component identifier present in the received packet to produce the comparison result. 
     
     
       20. The system of claim 19 wherein the comparator produces said predetermined signal when the identification value associated with said memory component does not match the identification value associated with the memory component identifier present in the received packet. 
     
     
       21. The system of claim 18 wherein the first operational mode comprises a low power consumption operational mode. 
     
     
       22. The system of claim 18 wherein the second operational mode comprises an active operational mode. 
     
     
       23. The system of claim 19 wherein said comparator is configured to produce a binary signal having logic states in response to match and non-match of the identification value associated with said memory component and the identification value associated with the memory component identifier present in the received packet, as said predetermined signal.